82 lines
2.0 KiB
Plaintext
82 lines
2.0 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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/**
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* DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1
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* and ENET-2 Expansion slots of J784S4 EVM.
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*
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* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy-cadence.h>
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#include <dt-bindings/phy/phy.h>
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#include "k3-serdes.h"
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&{/} {
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aliases {
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ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
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ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
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ethernet3 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
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};
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};
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&main_cpsw0 {
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pinctrl-names = "default";
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status = "okay";
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};
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&main_cpsw0_port1 {
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phy-mode = "usxgmii";
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mac-address = [00 00 00 00 00 00];
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phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>;
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phy-names = "mac", "serdes";
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status = "okay";
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fixed-link {
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speed = <5000>;
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full-duplex;
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};
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};
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&main_cpsw0_port2 {
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phy-mode = "usxgmii";
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mac-address = [00 00 00 00 00 00];
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phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>;
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phy-names = "mac", "serdes";
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status = "okay";
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fixed-link {
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speed = <5000>;
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full-duplex;
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};
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};
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&serdes_wiz2 {
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assigned-clock-parents = <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */
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status = "okay";
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};
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&serdes2 {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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serdes2_usxgmii_link: phy@2 {
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reg = <2>;
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cdns,num-lanes = <2>;
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#phy-cells = <0>;
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cdns,phy-type = <PHY_TYPE_USXGMII>;
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resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>;
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};
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};
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&serdes_ln_ctrl {
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idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>,
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<J784S4_SERDES0_LANE2_IP3_UNUSED>, <J784S4_SERDES0_LANE3_USB>,
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<J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>,
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<J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>,
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<J784S4_SERDES2_LANE0_IP2_UNUSED>, <J784S4_SERDES2_LANE1_IP2_UNUSED>,
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<J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>;
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};
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