99 lines
1.9 KiB
Plaintext
99 lines
1.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* Device Tree Source for J742S2 SoC Family
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*
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* TRM: https://www.ti.com/lit/pdf/spruje3
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*
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* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
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*
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*/
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#include "k3-j784s4-j742s2-common.dtsi"
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/ {
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model = "Texas Instruments K3 J742S2 SoC";
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compatible = "ti,j742s2";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0: cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a72";
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reg = <0x000>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&L2_0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a72";
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reg = <0x001>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&L2_0>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a72";
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reg = <0x002>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&L2_0>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a72";
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reg = <0x003>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0xc000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&L2_0>;
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};
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};
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};
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#include "k3-j742s2-main.dtsi"
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