619 lines
14 KiB
Plaintext
619 lines
14 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sm4450-camcc.h>
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#include <dt-bindings/clock/qcom,sm4450-dispcc.h>
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#include <dt-bindings/clock/qcom,sm4450-gcc.h>
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#include <dt-bindings/clock/qcom,sm4450-gpucc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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clock-frequency = <76800000>;
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#clock-cells = <0>;
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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bi_tcxo_div2: bi-tcxo-div2-clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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clocks = <&cpufreq_hw 0>;
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enable-method = "psci";
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next-level-cache = <&l2_0>;
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power-domains = <&cpu_pd0>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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#cooling-cells = <2>;
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l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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l3_0: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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};
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};
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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clocks = <&cpufreq_hw 0>;
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enable-method = "psci";
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next-level-cache = <&l2_100>;
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power-domains = <&cpu_pd0>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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#cooling-cells = <2>;
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l2_100: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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clocks = <&cpufreq_hw 0>;
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enable-method = "psci";
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next-level-cache = <&l2_200>;
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power-domains = <&cpu_pd0>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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#cooling-cells = <2>;
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l2_200: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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clocks = <&cpufreq_hw 0>;
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enable-method = "psci";
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next-level-cache = <&l2_300>;
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power-domains = <&cpu_pd0>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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#cooling-cells = <2>;
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l2_300: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x400>;
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clocks = <&cpufreq_hw 0>;
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enable-method = "psci";
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next-level-cache = <&l2_400>;
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power-domains = <&cpu_pd0>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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#cooling-cells = <2>;
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l2_400: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x500>;
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clocks = <&cpufreq_hw 0>;
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enable-method = "psci";
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next-level-cache = <&l2_500>;
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power-domains = <&cpu_pd0>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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#cooling-cells = <2>;
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l2_500: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x0 0x600>;
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clocks = <&cpufreq_hw 1>;
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enable-method = "psci";
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next-level-cache = <&l2_600>;
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power-domains = <&cpu_pd0>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 1>;
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#cooling-cells = <2>;
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l2_600: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x0 0x700>;
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clocks = <&cpufreq_hw 1>;
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enable-method = "psci";
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next-level-cache = <&l2_700>;
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power-domains = <&cpu_pd0>;
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power-domain-names = "psci";
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qcom,freq-domain = <&cpufreq_hw 1>;
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#cooling-cells = <2>;
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l2_700: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&l3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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core4 {
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cpu = <&cpu4>;
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};
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core5 {
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cpu = <&cpu5>;
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};
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core6 {
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cpu = <&cpu6>;
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};
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core7 {
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cpu = <&cpu7>;
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};
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};
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};
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idle-states {
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entry-method = "psci";
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little_cpu_sleep_0: cpu-sleep-0-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <800>;
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exit-latency-us = <750>;
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min-residency-us = <4090>;
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local-timer-stop;
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};
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big_cpu_sleep_0: cpu-sleep-1-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <600>;
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exit-latency-us = <1550>;
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min-residency-us = <4791>;
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local-timer-stop;
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};
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};
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domain-idle-states {
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cluster_sleep_0: cluster-sleep-0 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x41000044>;
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entry-latency-us = <1050>;
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exit-latency-us = <2500>;
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min-residency-us = <5309>;
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};
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cluster_sleep_1: cluster-sleep-1 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x41003344>;
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entry-latency-us = <1561>;
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exit-latency-us = <2801>;
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min-residency-us = <8550>;
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};
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};
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};
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memory@a0000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0xa0000000 0x0 0x0>;
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};
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pmu-a55 {
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compatible = "arm,cortex-a55-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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pmu-a78 {
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compatible = "arm,cortex-a78-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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cpu_pd0: power-domain-cpu0 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&little_cpu_sleep_0>;
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};
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cpu_pd1: power-domain-cpu1 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&little_cpu_sleep_0>;
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};
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cpu_pd2: power-domain-cpu2 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&little_cpu_sleep_0>;
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};
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cpu_pd3: power-domain-cpu3 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&little_cpu_sleep_0>;
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};
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cpu_pd4: power-domain-cpu4 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&big_cpu_sleep_0>;
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};
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cpu_pd5: power-domain-cpu5 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&big_cpu_sleep_0>;
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};
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cpu_pd6: power-domain-cpu6 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&big_cpu_sleep_0>;
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};
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cpu_pd7: power-domain-cpu7 {
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#power-domain-cells = <0>;
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power-domains = <&cluster_pd>;
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domain-idle-states = <&big_cpu_sleep_0>;
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};
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cluster_pd: power-domain-cpu-cluster0 {
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#power-domain-cells = <0>;
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domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>;
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};
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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aop_cmd_db_mem: cmd-db@80860000 {
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compatible = "qcom,cmd-db";
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reg = <0x0 0x80860000 0x0 0x20000>;
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no-map;
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};
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};
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soc: soc@0 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0 0x10 0>;
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dma-ranges = <0 0 0 0 0x10 0>;
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compatible = "simple-bus";
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gcc: clock-controller@100000 {
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compatible = "qcom,sm4450-gcc";
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reg = <0x0 0x00100000 0x0 0x1f4200>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>,
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<0>,
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<0>,
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<0>,
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<0>;
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};
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qupv3_id_0: geniqup@ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x00ac0000 0x0 0x2000>;
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ranges;
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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clock-names = "m-ahb", "s-ahb";
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#address-cells = <2>;
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#size-cells = <2>;
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status = "disabled";
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uart7: serial@a88000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x0 0x00a88000 0x0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
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pinctrl-names = "default";
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status = "disabled";
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};
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};
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tcsr_mutex: hwlock@1f40000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0x0 0x01f40000 0x0 0x40000>;
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#hwlock-cells = <1>;
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};
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gpucc: clock-controller@3d90000 {
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compatible = "qcom,sm4450-gpucc";
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reg = <0x0 0x03d90000 0x0 0xa000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_GPU_GPLL0_CLK_SRC>,
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<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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camcc: clock-controller@ade0000 {
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compatible = "qcom,sm4450-camcc";
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reg = <0x0 0x0ade0000 0x0 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_CAMERA_AHB_CLK>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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dispcc: clock-controller@af00000 {
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compatible = "qcom,sm4450-dispcc";
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reg = <0x0 0x0af00000 0x0 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&gcc GCC_DISP_AHB_CLK>,
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<&sleep_clk>,
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<0>,
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<0>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm4450-pdc", "qcom,pdc";
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reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
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qcom,pdc-ranges = <0 480 94>, <94 494 31>,
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<125 63 1>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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tlmm: pinctrl@f100000 {
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compatible = "qcom,sm4450-tlmm";
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reg = <0x0 0x0f100000 0x0 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 137>;
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wakeup-parent = <&pdc>;
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qup_uart7_rx: qup-uart7-rx-state {
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pins = "gpio23";
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function = "qup1_se2_l2";
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drive-strength = <2>;
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bias-disable;
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};
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qup_uart7_tx: qup-uart7-tx-state {
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pins = "gpio22";
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function = "qup1_se2_l2";
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drive-strength = <2>;
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bias-disable;
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};
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};
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intc: interrupt-controller@17200000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
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<0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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};
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timer@17420000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x17420000 0x0 0x1000>;
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ranges = <0 0 0 0x20000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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frame@17421000 {
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reg = <0x17421000 0x1000>,
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<0x17422000 0x1000>;
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
frame@17423000 {
|
|
reg = <0x17423000 0x1000>;
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17425000 {
|
|
reg = <0x17425000 0x1000>;
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17427000 {
|
|
reg = <0x17427000 0x1000>;
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17429000 {
|
|
reg = <0x17429000 0x1000>;
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1742b000 {
|
|
reg = <0x1742b000 0x1000>;
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1742d000 {
|
|
reg = <0x1742d000 0x1000>;
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
apps_rsc: rsc@17a00000 {
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x0 0x17a00000 0x0 0x10000>,
|
|
<0x0 0x17a10000 0x0 0x10000>,
|
|
<0x0 0x17a20000 0x0 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
label = "apps_rsc";
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
|
|
<WAKE_TCS 3>, <CONTROL_TCS 0>;
|
|
power-domains = <&cluster_pd>;
|
|
|
|
apps_bcm_voter: bcm-voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "qcom,sm4450-rpmh-clk";
|
|
#clock-cells = <1>;
|
|
clocks = <&xo_board>;
|
|
clock-names = "xo";
|
|
};
|
|
};
|
|
|
|
cpufreq_hw: cpufreq@17d91000 {
|
|
compatible = "qcom,sm4450-cpufreq-epss", "qcom,cpufreq-epss";
|
|
reg = <0 0x17d91000 0 0x1000>,
|
|
<0 0x17d92000 0 0x1000>;
|
|
reg-names = "freq-domain0", "freq-domain1";
|
|
clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
|
|
#freq-domain-cells = <1>;
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|