265 lines
6.9 KiB
Plaintext
265 lines
6.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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#include <dt-bindings/clock/mediatek,mt7988-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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compatible = "mediatek,mt7988a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a73";
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reg = <0x0>;
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device_type = "cpu";
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enable-method = "psci";
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};
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cpu@1 {
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compatible = "arm,cortex-a73";
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reg = <0x1>;
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device_type = "cpu";
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enable-method = "psci";
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};
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cpu@2 {
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compatible = "arm,cortex-a73";
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reg = <0x2>;
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device_type = "cpu";
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enable-method = "psci";
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};
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cpu@3 {
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compatible = "arm,cortex-a73";
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reg = <0x3>;
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device_type = "cpu";
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enable-method = "psci";
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};
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};
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oscillator-40m {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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#clock-cells = <0>;
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clock-output-names = "clkxtal";
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};
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pmu {
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compatible = "arm,cortex-a73-pmu";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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soc {
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compatible = "simple-bus";
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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reg = <0 0x0c000000 0 0x40000>, /* GICD */
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<0 0x0c080000 0 0x200000>, /* GICR */
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<0 0x0c400000 0 0x2000>, /* GICC */
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<0 0x0c410000 0 0x1000>, /* GICH */
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<0 0x0c420000 0 0x2000>; /* GICV */
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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infracfg: clock-controller@10001000 {
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compatible = "mediatek,mt7988-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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};
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topckgen: clock-controller@1001b000 {
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compatible = "mediatek,mt7988-topckgen", "syscon";
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reg = <0 0x1001b000 0 0x1000>;
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#clock-cells = <1>;
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};
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watchdog: watchdog@1001c000 {
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compatible = "mediatek,mt7988-wdt";
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reg = <0 0x1001c000 0 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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#reset-cells = <1>;
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};
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clock-controller@1001e000 {
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compatible = "mediatek,mt7988-apmixedsys";
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reg = <0 0x1001e000 0 0x1000>;
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#clock-cells = <1>;
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};
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pwm@10048000 {
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compatible = "mediatek,mt7988-pwm";
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reg = <0 0x10048000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
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<&infracfg CLK_INFRA_66M_PWM_HCK>,
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<&infracfg CLK_INFRA_66M_PWM_CK1>,
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<&infracfg CLK_INFRA_66M_PWM_CK2>,
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<&infracfg CLK_INFRA_66M_PWM_CK3>,
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<&infracfg CLK_INFRA_66M_PWM_CK4>,
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<&infracfg CLK_INFRA_66M_PWM_CK5>,
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<&infracfg CLK_INFRA_66M_PWM_CK6>,
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<&infracfg CLK_INFRA_66M_PWM_CK7>,
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<&infracfg CLK_INFRA_66M_PWM_CK8>;
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clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
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"pwm4", "pwm5", "pwm6", "pwm7", "pwm8";
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#pwm-cells = <2>;
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status = "disabled";
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};
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serial@11000000 {
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compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
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reg = <0 0x11000000 0 0x100>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "uart", "wakeup";
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_52M_UART0_CK>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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serial@11000100 {
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compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
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reg = <0 0x11000100 0 0x100>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "uart", "wakeup";
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_52M_UART1_CK>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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serial@11000200 {
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compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
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reg = <0 0x11000200 0 0x100>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "uart", "wakeup";
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_52M_UART2_CK>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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i2c@11003000 {
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compatible = "mediatek,mt7981-i2c";
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reg = <0 0x11003000 0 0x1000>,
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<0 0x10217080 0 0x80>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_I2C_BCK>,
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<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c@11004000 {
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compatible = "mediatek,mt7981-i2c";
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reg = <0 0x11004000 0 0x1000>,
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<0 0x10217100 0 0x80>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_I2C_BCK>,
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<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c@11005000 {
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compatible = "mediatek,mt7981-i2c";
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reg = <0 0x11005000 0 0x1000>,
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<0 0x10217180 0 0x80>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_I2C_BCK>,
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<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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usb@11190000 {
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compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
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reg = <0 0x11190000 0 0x2e00>,
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<0 0x11193e00 0 0x0100>;
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reg-names = "mac", "ippc";
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interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_USB_SYS>,
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<&infracfg CLK_INFRA_USB_REF>,
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<&infracfg CLK_INFRA_66M_USB_HCK>,
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<&infracfg CLK_INFRA_133M_USB_HCK>,
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<&infracfg CLK_INFRA_USB_XHCI>;
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clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
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};
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usb@11200000 {
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compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
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reg = <0 0x11200000 0 0x2e00>,
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<0 0x11203e00 0 0x0100>;
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reg-names = "mac", "ippc";
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interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
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<&infracfg CLK_INFRA_USB_CK_P1>,
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<&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
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<&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>,
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<&infracfg CLK_INFRA_USB_XHCI_CK_P1>;
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clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
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};
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clock-controller@11f40000 {
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compatible = "mediatek,mt7988-xfi-pll";
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reg = <0 0x11f40000 0 0x1000>;
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resets = <&watchdog 16>;
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#clock-cells = <1>;
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};
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efuse@11f50000 {
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compatible = "mediatek,mt7988-efuse", "mediatek,efuse";
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reg = <0 0x11f50000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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clock-controller@15000000 {
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compatible = "mediatek,mt7988-ethsys", "syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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clock-controller@15031000 {
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compatible = "mediatek,mt7988-ethwarp";
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reg = <0 0x15031000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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