376 lines
6.8 KiB
Plaintext
376 lines
6.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
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*
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* DTS for SolidRun CN9130 Clearfog Pro.
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*
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include "cn9130.dtsi"
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#include "cn9130-sr-som.dtsi"
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#include "cn9130-cf.dtsi"
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/ {
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model = "SolidRun CN9130 Clearfog Pro";
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compatible = "solidrun,cn9130-clearfog-pro",
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"solidrun,cn9130-sr-som", "marvell,cn9130";
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&rear_button_pins>;
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pinctrl-names = "default";
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button-0 {
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/* The rear SW3 button */
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label = "Rear Button";
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gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
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linux,can-disable;
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linux,code = <BTN_0>;
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};
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};
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};
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/* SRDS #3 - SGMII 1GE to L2 switch */
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&cp0_eth1 {
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phys = <&cp0_comphy3 1>;
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phy-mode = "sgmii";
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status = "okay";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&cp0_eth2_phy {
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/*
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* Configure LEDs default behaviour similar to switch ports:
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* - LED[0]: link/activity: On/blink (green)
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* - LED[1]: link is 100/1000Mbps: On (red)
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* - LED[2]: high impedance (floating)
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*
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* Switch port defaults:
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* - LED0: link/activity: On/blink (green)
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* - LED1: link is 1000Mbps: On (red)
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*
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* Identical configuration is impossible with hardware offload.
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*/
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marvell,reg-init = <3 16 0xf000 0x0a61>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_WAN;
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label = "LED2";
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_WAN;
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label = "LED1";
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default-state = "keep";
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};
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};
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};
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&cp0_mdio {
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ethernet-switch@4 {
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compatible = "marvell,mv88e6085";
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reg = <4>;
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pinctrl-0 = <&dsa_clk_pins &dsa_pins>;
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pinctrl-names = "default";
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reset-gpios = <&cp0_gpio1 27 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&cp0_gpio1>;
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interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-port@0 {
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reg = <0>;
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label = "lan5";
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phy = <&switch0phy0>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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label = "LED12";
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_LAN;
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label = "LED11";
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default-state = "keep";
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};
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};
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};
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ethernet-port@1 {
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reg = <1>;
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label = "lan4";
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phy = <&switch0phy1>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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label = "LED10";
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_LAN;
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label = "LED9";
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default-state = "keep";
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};
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};
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};
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ethernet-port@2 {
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reg = <2>;
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label = "lan3";
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phy = <&switch0phy2>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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label = "LED8";
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_LAN;
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label = "LED7";
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default-state = "keep";
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};
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};
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};
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ethernet-port@3 {
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reg = <3>;
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label = "lan2";
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phy = <&switch0phy3>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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label = "LED6";
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_LAN;
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label = "LED5";
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default-state = "keep";
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};
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};
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};
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ethernet-port@4 {
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reg = <4>;
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label = "lan1";
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phy = <&switch0phy4>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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label = "LED4";
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_LAN;
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label = "LED3";
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default-state = "keep";
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};
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};
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};
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ethernet-port@5 {
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reg = <5>;
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label = "cpu";
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ethernet = <&cp0_eth1>;
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phy-mode = "sgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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ethernet-port@6 {
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reg = <6>;
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label = "lan6";
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phy-mode = "rgmii";
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/*
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* Because of mdio address conflict the
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* external phy is not readable.
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* Force a fixed link instead.
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*/
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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switch0phy1: ethernet-phy@1 {
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reg = <0x1>;
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/*
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* Indirectly configure default behaviour
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* for port lan6 leds behind external phy.
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* Internal PHYs are not using page 3,
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* therefore writing to it is safe.
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*/
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marvell,reg-init = <3 16 0xf000 0x0a61>;
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};
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switch0phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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switch0phy3: ethernet-phy@3 {
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reg = <0x3>;
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};
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switch0phy4: ethernet-phy@4 {
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reg = <0x4>;
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};
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};
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/*
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* There is an external phy on the switch mdio bus.
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* Because its mdio address collides with internal phys,
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* it is not readable.
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*
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* mdio-external {
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* compatible = "marvell,mv88e6xxx-mdio-external";
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* #address-cells = <1>;
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* #size-cells = <0>;
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*
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* ethernet-phy@1 {
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* reg = <0x1>;
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* };
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* };
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*/
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};
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};
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/* SRDS #4 - miniPCIe (CON2) */
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&cp0_pcie1 {
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num-lanes = <1>;
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phys = <&cp0_comphy4 1>;
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/* dw-pcie inverts internally */
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reset-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&cp0_pinctrl {
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dsa_clk_pins: cp0-dsa-clk-pins {
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marvell,pins = "mpp40";
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marvell,function = "synce1";
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};
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dsa_pins: cp0-dsa-pins {
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marvell,pins = "mpp27", "mpp29";
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marvell,function = "gpio";
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};
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rear_button_pins: cp0-rear-button-pins {
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marvell,pins = "mpp32";
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marvell,function = "gpio";
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};
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cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
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marvell,pins = "mpp12";
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marvell,function = "spi1";
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};
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};
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&cp0_spi1 {
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/* add pin for chip-select 1 on mikrobus */
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pinctrl-0 = <&cp0_spi1_pins &cp0_spi1_cs1_pins>;
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};
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/* USB-2.0 Host on Type-A connector */
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&cp0_usb3_1 {
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phys = <&cp0_utmi1>;
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phy-names = "utmi";
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dr_mode = "host";
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status = "okay";
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};
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&expander0 {
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/* CON2 */
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pcie1-0-clkreq-hog {
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gpio-hog;
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gpios = <4 GPIO_ACTIVE_LOW>;
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input;
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line-name = "pcie1.0-clkreq";
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};
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/* CON2 */
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pcie1-0-w-disable-hog {
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gpio-hog;
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gpios = <7 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "pcie1.0-w-disable";
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};
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};
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