367 lines
6.8 KiB
Plaintext
367 lines
6.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* NXP S32G2 SoC family
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*
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* Copyright (c) 2021 SUSE LLC
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* Copyright 2017-2021, 2024 NXP
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "nxp,s32g2";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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scmi_buf: shm@d0000000 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0xd0000000 0x0 0x80>;
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no-map;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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next-level-cache = <&cluster0_l2>;
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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enable-method = "psci";
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next-level-cache = <&cluster1_l2>;
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};
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cluster0_l2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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cluster1_l2: l2-cache1 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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firmware {
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scmi {
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compatible = "arm,scmi-smc";
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arm,smc-id = <0xc20000fe>;
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#address-cells = <1>;
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#size-cells = <0>;
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shmem = <&scmi_buf>;
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clks: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0x80000000>;
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pinctrl: pinctrl@4009c240 {
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compatible = "nxp,s32g2-siul2-pinctrl";
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/* MSCR0-MSCR101 registers on siul2_0 */
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reg = <0x4009c240 0x198>,
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/* MSCR112-MSCR122 registers on siul2_1 */
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<0x44010400 0x2c>,
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/* MSCR144-MSCR190 registers on siul2_1 */
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<0x44010480 0xbc>,
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/* IMCR0-IMCR83 registers on siul2_0 */
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<0x4009ca40 0x150>,
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/* IMCR119-IMCR397 registers on siul2_1 */
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<0x44010c1c 0x45c>,
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/* IMCR430-IMCR495 registers on siul2_1 */
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<0x440110f8 0x108>;
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jtag_pins: jtag-pins {
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jtag-grp0 {
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pinmux = <0x0>;
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input-enable;
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bias-pull-up;
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slew-rate = <166>;
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};
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jtag-grp1 {
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pinmux = <0x11>;
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slew-rate = <166>;
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};
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jtag-grp2 {
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pinmux = <0x40>;
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input-enable;
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bias-pull-down;
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slew-rate = <166>;
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};
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jtag-grp3 {
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pinmux = <0x23c0>,
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<0x23d0>,
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<0x2320>;
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};
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jtag-grp4 {
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pinmux = <0x51>;
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input-enable;
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bias-pull-up;
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slew-rate = <166>;
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};
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};
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pinctrl_usdhc0: usdhc0grp-pins {
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usdhc0-grp0 {
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pinmux = <0x2e1>,
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<0x381>;
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output-enable;
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bias-pull-down;
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slew-rate = <150>;
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};
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usdhc0-grp1 {
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pinmux = <0x2f1>,
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<0x301>,
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<0x311>,
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<0x321>,
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<0x331>,
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<0x341>,
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<0x351>,
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<0x361>,
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<0x371>;
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output-enable;
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input-enable;
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bias-pull-up;
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slew-rate = <150>;
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};
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usdhc0-grp2 {
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pinmux = <0x391>;
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output-enable;
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slew-rate = <150>;
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};
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usdhc0-grp3 {
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pinmux = <0x3a0>;
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input-enable;
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slew-rate = <150>;
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};
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usdhc0-grp4 {
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pinmux = <0x2032>,
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<0x2042>,
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<0x2052>,
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<0x2062>,
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<0x2072>,
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<0x2082>,
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<0x2092>,
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<0x20a2>,
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<0x20b2>,
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<0x20c2>;
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};
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};
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pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {
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usdhc0-100mhz-grp0 {
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pinmux = <0x2e1>,
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<0x381>;
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output-enable;
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bias-pull-down;
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slew-rate = <150>;
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};
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usdhc0-100mhz-grp1 {
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pinmux = <0x2f1>,
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<0x301>,
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<0x311>,
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<0x321>,
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<0x331>,
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<0x341>,
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<0x351>,
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<0x361>,
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<0x371>;
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output-enable;
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input-enable;
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bias-pull-up;
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slew-rate = <150>;
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};
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usdhc0-100mhz-grp2 {
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pinmux = <0x391>;
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output-enable;
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slew-rate = <150>;
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};
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usdhc0-100mhz-grp3 {
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pinmux = <0x3a0>;
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input-enable;
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slew-rate = <150>;
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};
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usdhc0-100mhz-grp4 {
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pinmux = <0x2032>,
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<0x2042>,
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<0x2052>,
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<0x2062>,
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<0x2072>,
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<0x2082>,
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<0x2092>,
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<0x20a2>,
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<0x20b2>,
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<0x20c2>;
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};
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};
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pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {
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usdhc0-200mhz-grp0 {
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pinmux = <0x2e1>,
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<0x381>;
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output-enable;
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bias-pull-down;
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slew-rate = <208>;
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};
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usdhc0-200mhz-grp1 {
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pinmux = <0x2f1>,
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<0x301>,
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<0x311>,
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<0x321>,
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<0x331>,
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<0x341>,
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<0x351>,
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<0x361>,
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<0x371>;
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output-enable;
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input-enable;
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bias-pull-up;
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slew-rate = <208>;
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};
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usdhc0-200mhz-grp2 {
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pinmux = <0x391>;
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output-enable;
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slew-rate = <208>;
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};
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usdhc0-200mhz-grp3 {
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pinmux = <0x3a0>;
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input-enable;
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slew-rate = <208>;
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};
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usdhc0-200mhz-grp4 {
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pinmux = <0x2032>,
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<0x2042>,
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<0x2052>,
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<0x2062>,
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<0x2072>,
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<0x2082>,
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<0x2092>,
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<0x20a2>,
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<0x20b2>,
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<0x20c2>;
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};
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};
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};
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uart0: serial@401c8000 {
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compatible = "nxp,s32g2-linflexuart",
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"fsl,s32v234-linflexuart";
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reg = <0x401c8000 0x3000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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uart1: serial@401cc000 {
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compatible = "nxp,s32g2-linflexuart",
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"fsl,s32v234-linflexuart";
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reg = <0x401cc000 0x3000>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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uart2: serial@402bc000 {
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compatible = "nxp,s32g2-linflexuart",
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"fsl,s32v234-linflexuart";
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reg = <0x402bc000 0x3000>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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usdhc0: mmc@402f0000 {
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compatible = "nxp,s32g2-usdhc";
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reg = <0x402f0000 0x1000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 32>, <&clks 31>, <&clks 33>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <8>;
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status = "disabled";
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};
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gic: interrupt-controller@50800000 {
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compatible = "arm,gic-v3";
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reg = <0x50800000 0x10000>,
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<0x50880000 0x80000>,
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<0x50400000 0x2000>,
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<0x50410000 0x2000>,
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<0x50420000 0x2000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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};
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};
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