77 lines
1.9 KiB
Plaintext
77 lines
1.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2024 NXP
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*/
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&qm_lvds0_lis_lpcg {
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clocks = <&lvds_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_4>;
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};
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&qm_lvds0_pwm_lpcg {
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clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>,
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<&lvds_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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};
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&qm_lvds0_i2c0_lpcg {
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clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>,
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<&lvds_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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};
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&qm_pwm_lvds0 {
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clocks = <&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_4>,
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<&qm_lvds0_pwm_lpcg IMX_LPCG_CLK_0>;
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};
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&qm_i2c0_lvds0 {
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clocks = <&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_0>,
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<&qm_lvds0_i2c0_lpcg IMX_LPCG_CLK_4>;
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};
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&lvds0_subsys {
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interrupt-parent = <&irqsteer_lvds0>;
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irqsteer_lvds0: interrupt-controller@56240000 {
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compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
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reg = <0x56240000 0x1000>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <1>;
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clocks = <&qm_lvds0_lis_lpcg IMX_LPCG_CLK_4>;
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clock-names = "ipg";
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power-domains = <&pd IMX_SC_R_LVDS_0>;
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fsl,channel = <0>;
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fsl,num-irqs = <32>;
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};
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lvds0_i2c1_lpcg: clock-controller@56243014 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x56243014 0x4>;
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#clock-cells = <1>;
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clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>,
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<&lvds_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "lvds0_i2c1_lpcg_clk",
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"lvds0_i2c1_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
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};
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i2c1_lvds0: i2c@56247000 {
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compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
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reg = <0x56247000 0x1000>;
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interrupts = <9>;
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clocks = <&lvds0_i2c1_lpcg IMX_LPCG_CLK_0>,
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<&lvds0_i2c1_lpcg IMX_LPCG_CLK_4>;
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clock-names = "per", "ipg";
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assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>;
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assigned-clock-rates = <24000000>;
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power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
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status = "disabled";
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};
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};
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