150 lines
4.3 KiB
YAML
150 lines
4.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip USBDP Combo PHY with Samsung IP block
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maintainers:
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- Frank Wang <frank.wang@rock-chips.com>
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- Zhang Yubing <yubing.zhang@rock-chips.com>
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properties:
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compatible:
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enum:
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- rockchip,rk3576-usbdp-phy
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- rockchip,rk3588-usbdp-phy
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reg:
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maxItems: 1
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"#phy-cells":
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description: |
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Cell allows setting the type of the PHY. Possible values are:
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- PHY_TYPE_USB3
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- PHY_TYPE_DP
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const: 1
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: refclk
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- const: immortal
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- const: pclk
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- const: utmi
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resets:
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maxItems: 5
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reset-names:
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items:
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- const: init
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- const: cmn
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- const: lane
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- const: pcs_apb
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- const: pma_apb
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rockchip,dp-lane-mux:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 2
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maxItems: 4
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items:
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maximum: 3
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description:
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An array of physical Type-C lanes indexes. Position of an entry
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determines the DisplayPort (DP) lane index, while the value of an entry
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indicates physical Type-C lane. The supported DP lanes number are 2 or 4.
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e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = <2,
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3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
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lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux =
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<0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
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phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
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DP lanes are mapped by DisplayPort Alt mode, this property is not needed.
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rockchip,u2phy-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon managing the 'usb2 phy general register files'.
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rockchip,usb-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon managing the 'usb general register files'.
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rockchip,usbdpphy-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon managing the 'usbdp phy general register files'.
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rockchip,vo-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon managing the 'video output general register files'.
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When select the DP lane mapping will request its phandle.
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sbu1-dc-gpios:
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description:
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GPIO connected to the SBU1 line of the USB-C connector via a big resistor
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(~100K) to apply a DC offset for signalling the connector orientation.
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maxItems: 1
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sbu2-dc-gpios:
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description:
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GPIO connected to the SBU2 line of the USB-C connector via a big resistor
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(~100K) to apply a DC offset for signalling the connector orientation.
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maxItems: 1
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orientation-switch:
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description: Flag the port as possible handler of orientation switching
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type: boolean
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mode-switch:
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description: Flag the port as possible handler of altmode switching
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type: boolean
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port:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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A port node to link the PHY to a TypeC controller for the purpose of
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handling orientation switching.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rockchip,rk3588-cru.h>
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#include <dt-bindings/reset/rockchip,rk3588-cru.h>
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usbdp_phy0: phy@fed80000 {
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compatible = "rockchip,rk3588-usbdp-phy";
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reg = <0xfed80000 0x10000>;
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#phy-cells = <1>;
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clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
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<&cru CLK_USBDP_PHY0_IMMORTAL>,
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<&cru PCLK_USBDPPHY0>,
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<&u2phy0>;
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clock-names = "refclk", "immortal", "pclk", "utmi";
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resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
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<&cru SRST_USBDP_COMBO_PHY0_CMN>,
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<&cru SRST_USBDP_COMBO_PHY0_LANE>,
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<&cru SRST_USBDP_COMBO_PHY0_PCS>,
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<&cru SRST_P_USBDPPHY0>;
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reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
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rockchip,u2phy-grf = <&usb2phy0_grf>;
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rockchip,usb-grf = <&usb_grf>;
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rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
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rockchip,vo-grf = <&vo0_grf>;
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};
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