211 lines
5.7 KiB
YAML
211 lines
5.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/fsl,fman.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Frame Manager Device
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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description:
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Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
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etc.) the FMan node will have child nodes for each of them.
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properties:
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compatible:
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enum:
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- fsl,fman
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description:
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FMan version can be determined via FM_IP_REV_1 register in the
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FMan block. The offset is 0xc4 from the beginning of the
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Frame Processing Manager memory map (0xc3000 from the
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beginning of the FMan node).
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cell-index:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Specifies the index of the FMan unit.
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The cell-index value may be used by the SoC, to identify the
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FMan unit in the SoC memory map. In the table below,
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there's a description of the cell-index use in each SoC:
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- P1023:
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register[bit] FMan unit cell-index
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============================================================
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DEVDISR[1] 1 0
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- P2041, P3041, P4080 P5020, P5040:
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register[bit] FMan unit cell-index
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============================================================
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DCFG_DEVDISR2[6] 1 0
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DCFG_DEVDISR2[14] 2 1
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(Second FM available only in P4080 and P5040)
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- B4860, T1040, T2080, T4240:
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register[bit] FMan unit cell-index
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============================================================
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DCFG_CCSR_DEVDISR2[24] 1 0
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DCFG_CCSR_DEVDISR2[25] 2 1
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(Second FM available only in T4240)
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DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
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the specific SoC "Device Configuration/Pin Control" Memory
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Map.
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reg:
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items:
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- description: BMI configuration registers.
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- description: QMI configuration registers.
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- description: DMA configuration registers.
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- description: FPM configuration registers.
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- description: FMan controller configuration registers.
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minItems: 1
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ranges: true
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: fmanclk
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interrupts:
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items:
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- description: The first element is associated with the event interrupts.
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- description: the second element is associated with the error interrupts.
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dma-coherent: true
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ptimer-handle:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: see ptp/fsl,ptp.yaml
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fsl,qman-channel-range:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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Specifies the range of the available dedicated
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channels in the FMan. The first cell specifies the beginning
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of the range and the second cell specifies the number of
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channels
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items:
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- description: The first cell specifies the beginning of the range.
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- description: |
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The second cell specifies the number of channels.
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Further information available at:
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"Work Queue (WQ) Channel Assignments in the QMan" section
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in DPAA Reference Manual.
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fsl,qman:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: See soc/fsl/qman.txt
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fsl,bman:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: See soc/fsl/bman.txt
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fsl,erratum-a050385:
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$ref: /schemas/types.yaml#/definitions/flag
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description: A boolean property. Indicates the presence of the
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erratum A050385 which indicates that DMA transactions that are
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split can result in a FMan lock.
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'#address-cells':
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const: 1
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'#size-cells':
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const: 1
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patternProperties:
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'^muram@[a-f0-9]+$':
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$ref: fsl,fman-muram.yaml
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'^port@[a-f0-9]+$':
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$ref: fsl,fman-port.yaml
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'^ethernet@[a-f0-9]+$':
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$ref: fsl,fman-dtsec.yaml
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'^mdio@[a-f0-9]+$':
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$ref: fsl,fman-mdio.yaml
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'^phc@[a-f0-9]+$':
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$ref: /schemas/ptp/fsl,ptp.yaml
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required:
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- compatible
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- cell-index
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- reg
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- ranges
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- clocks
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- clock-names
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- interrupts
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- fsl,qman-channel-range
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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fman@400000 {
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compatible = "fsl,fman";
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reg = <0x400000 0x100000>;
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ranges = <0 0x400000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <1>;
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clocks = <&fman_clk>;
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clock-names = "fmanclk";
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interrupts = <96 IRQ_TYPE_EDGE_FALLING>,
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<16 IRQ_TYPE_EDGE_FALLING>;
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fsl,qman-channel-range = <0x40 0xc>;
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muram@0 {
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compatible = "fsl,fman-muram";
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reg = <0x0 0x28000>;
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};
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port@81000 {
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cell-index = <1>;
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compatible = "fsl,fman-v2-port-oh";
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reg = <0x81000 0x1000>;
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};
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fman1_rx_0x8: port@88000 {
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cell-index = <0x8>;
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compatible = "fsl,fman-v2-port-rx";
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reg = <0x88000 0x1000>;
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};
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fman1_tx_0x28: port@a8000 {
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cell-index = <0x28>;
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compatible = "fsl,fman-v2-port-tx";
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reg = <0xa8000 0x1000>;
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};
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ethernet@e0000 {
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compatible = "fsl,fman-dtsec";
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cell-index = <0>;
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reg = <0xe0000 0x1000>;
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ptp-timer = <&ptp_timer>;
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fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
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tbi-handle = <&tbi5>;
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};
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ptp_timer: phc@fe000 {
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compatible = "fsl,fman-ptp-timer";
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reg = <0xfe000 0x1000>;
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interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
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};
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mdio@f1000 {
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compatible = "fsl,fman-xmdio";
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reg = <0xf1000 0x1000>;
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interrupts = <101 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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