88 lines
1.9 KiB
YAML
88 lines
1.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/nuvoton,ma35d1-sdhci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Nuvoton MA35D1 SD/SDIO/MMC Controller
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maintainers:
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- Shan-Chun Hung <shanchun1218@gmail.com>
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allOf:
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- $ref: sdhci-common.yaml#
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properties:
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compatible:
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enum:
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- nuvoton,ma35d1-sdhci
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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pinctrl-names:
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minItems: 1
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items:
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- const: default
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- const: state_uhs
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pinctrl-0:
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description:
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Should contain default/high speed pin ctrl.
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maxItems: 1
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pinctrl-1:
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description:
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Should contain uhs mode pin ctrl.
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maxItems: 1
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resets:
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maxItems: 1
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nuvoton,sys:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to access GCR (Global Control Register) registers.
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- pinctrl-names
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- pinctrl-0
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- resets
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- nuvoton,sys
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
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#include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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mmc@40190000 {
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compatible = "nuvoton,ma35d1-sdhci";
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reg = <0x0 0x40190000 0x0 0x2000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk SDH1_GATE>;
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&pinctrl_sdhci1>;
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pinctrl-1 = <&pinctrl_sdhci1_uhs>;
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resets = <&sys MA35D1_RESET_SDH1>;
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nuvoton,sys = <&sys>;
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vqmmc-supply = <&sdhci1_vqmmc_regulator>;
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bus-width = <8>;
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max-frequency = <200000000>;
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};
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};
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