148 lines
4.5 KiB
YAML
148 lines
4.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: RISC-V IOMMU Architecture Implementation
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maintainers:
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- Tomasz Jeznach <tjeznach@rivosinc.com>
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description: |
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The RISC-V IOMMU provides memory address translation and isolation for
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input and output devices, supporting per-device translation context,
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shared process address spaces including the ATS and PRI components of
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the PCIe specification, two stage address translation and MSI remapping.
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It supports identical translation table format to the RISC-V address
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translation tables with page level access and protection attributes.
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Hardware uses in-memory command and fault reporting queues with wired
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interrupt or MSI notifications.
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Visit https://github.com/riscv-non-isa/riscv-iommu for more details.
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For information on assigning RISC-V IOMMU to its peripheral devices,
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see generic IOMMU bindings.
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properties:
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# For PCIe IOMMU hardware compatible property should contain the vendor
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# and device ID according to the PCI Bus Binding specification.
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# Since PCI provides built-in identification methods, compatible is not
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# actually required. For non-PCIe hardware implementations 'riscv,iommu'
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# should be specified along with 'reg' property providing MMIO location.
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compatible:
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oneOf:
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- items:
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- enum:
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- qemu,riscv-iommu
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- const: riscv,iommu
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- items:
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- enum:
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- pci1efd,edf1
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- const: riscv,pci-iommu
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reg:
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maxItems: 1
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description:
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For non-PCI devices this represents base address and size of for the
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IOMMU memory mapped registers interface.
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For PCI IOMMU hardware implementation this should represent an address
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of the IOMMU, as defined in the PCI Bus Binding reference.
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'#iommu-cells':
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const: 1
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description:
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The single cell describes the requester id emitted by a master to the
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IOMMU.
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interrupts:
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minItems: 1
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maxItems: 4
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description:
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Wired interrupt vectors available for RISC-V IOMMU to notify the
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RISC-V HARTS. The cause to interrupt vector is software defined
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using IVEC IOMMU register.
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msi-parent: true
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- '#iommu-cells'
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additionalProperties: false
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examples:
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- |+
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/* Example 1 (IOMMU device with wired interrupts) */
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#include <dt-bindings/interrupt-controller/irq.h>
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iommu1: iommu@1bccd000 {
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compatible = "qemu,riscv-iommu", "riscv,iommu";
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reg = <0x1bccd000 0x1000>;
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interrupt-parent = <&aplic_smode>;
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interrupts = <32 IRQ_TYPE_LEVEL_HIGH>,
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<33 IRQ_TYPE_LEVEL_HIGH>,
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<34 IRQ_TYPE_LEVEL_HIGH>,
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<35 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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};
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/* Device with two IOMMU device IDs, 0 and 7 */
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master1 {
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iommus = <&iommu1 0>, <&iommu1 7>;
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};
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- |+
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/* Example 2 (IOMMU device with shared wired interrupt) */
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#include <dt-bindings/interrupt-controller/irq.h>
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iommu2: iommu@1bccd000 {
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compatible = "qemu,riscv-iommu", "riscv,iommu";
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reg = <0x1bccd000 0x1000>;
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interrupt-parent = <&aplic_smode>;
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interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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};
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- |+
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/* Example 3 (IOMMU device with MSIs) */
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iommu3: iommu@1bcdd000 {
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compatible = "qemu,riscv-iommu", "riscv,iommu";
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reg = <0x1bccd000 0x1000>;
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msi-parent = <&imsics_smode>;
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#iommu-cells = <1>;
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};
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- |+
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/* Example 4 (IOMMU PCIe device with MSIs) */
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@30000000 {
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x0 0x30000000 0x0 0x1000000>;
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ranges = <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x0f000000>;
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/*
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* The IOMMU manages all functions in this PCI domain except
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* itself. Omit BDF 00:01.0.
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*/
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iommu-map = <0x0 &iommu0 0x0 0x8>,
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<0x9 &iommu0 0x9 0xfff7>;
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/* The IOMMU programming interface uses slot 00:01.0 */
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iommu0: iommu@1,0 {
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compatible = "pci1efd,edf1", "riscv,pci-iommu";
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reg = <0x800 0 0 0 0>;
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#iommu-cells = <1>;
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};
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};
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};
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