63 lines
1.3 KiB
YAML
63 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Amlogic C3 series PLL Clock Controller
|
|
|
|
maintainers:
|
|
- Neil Armstrong <neil.armstrong@linaro.org>
|
|
- Jerome Brunet <jbrunet@baylibre.com>
|
|
- Chuan Liu <chuan.liu@amlogic.com>
|
|
- Xianwei Zhao <xianwei.zhao@amlogic.com>
|
|
|
|
properties:
|
|
compatible:
|
|
const: amlogic,c3-pll-clkc
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
items:
|
|
- description: input top pll
|
|
- description: input mclk pll
|
|
- description: input fix pll
|
|
|
|
clock-names:
|
|
items:
|
|
- const: top
|
|
- const: mclk
|
|
- const: fix
|
|
|
|
"#clock-cells":
|
|
const: 1
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- clocks
|
|
- clock-names
|
|
- "#clock-cells"
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
apb {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
clock-controller@8000 {
|
|
compatible = "amlogic,c3-pll-clkc";
|
|
reg = <0x0 0x8000 0x0 0x1a4>;
|
|
clocks = <&scmi_clk 2>,
|
|
<&scmi_clk 5>,
|
|
<&scmi_clk 12>;
|
|
clock-names = "top", "mclk", "fix";
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|