240 lines
7.8 KiB
YAML
240 lines
7.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bus/qcom,ebi2.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm External Bus Interface 2 (EBI2)
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description: |
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The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
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external memory (such as NAND or other memory-mapped peripherals) whereas
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LCDC handles LCD displays.
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As it says it connects devices to an external bus interface, meaning address
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lines (up to 9 address lines so can only address 1KiB external memory space),
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data lines (16 bits), OE (output enable), ADV (address valid, used on some
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NOR flash memories), WE (write enable). This on top of 6 different chip selects
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(CS0 thru CS5) so that in theory 6 different devices can be connected.
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Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
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and the bus can only come out on these pins, however if some of the pins are
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unused they can be left unconnected or remuxed to be used as GPIO or in some
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cases other orthogonal functions as well.
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Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
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The chip selects have the following memory range assignments. This region of
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memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
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Chip Select Physical address base
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CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
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CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
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CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
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CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
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CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
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CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
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The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
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August 6, 2012 contains some incomplete documentation of the EBI2.
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FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
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We have not been able to figure out which bit fields these correspond to
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in the hardware, or what valid values exist. The current hypothesis is that
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this is something just used on the FAST chip selects and that the SLOW
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chip selects are understood fully. There is also a "byte device enable"
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flag somewhere for 8bit memories.
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FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit
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unclear what this means, if they are mutually exclusive or can be used
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together, or if some chip selects are hardwired to be FAST and others are SLOW
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by design.
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The XMEM registers are totally undocumented but could be partially decoded
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because the Cypress AN49576 Antioch Westbridge apparently has suspiciously
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similar register layout, see: http://www.cypress.com/file/105771/download
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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properties:
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compatible:
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enum:
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- qcom,apq8060-ebi2
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- qcom,msm8660-ebi2
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reg:
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items:
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- description: EBI2 config region
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- description: XMEM config region
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reg-names:
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items:
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- const: ebi2
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- const: xmem
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ranges: true
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clocks:
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items:
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- description: EBI_2X clock
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- description: EBI clock
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clock-names:
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items:
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- const: ebi2x
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- const: ebi2
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'#address-cells':
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const: 2
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'#size-cells':
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const: 1
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required:
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- compatible
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- reg
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- reg-names
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- ranges
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- clocks
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- clock-names
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- '#address-cells'
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- '#size-cells'
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patternProperties:
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"^.*@[0-5],[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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reg:
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maxItems: 1
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# SLOW chip selects
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qcom,xmem-recovery-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The time the memory continues to drive the data bus after OE
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is de-asserted, in order to avoid contention on the data bus.
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They are inserted when reading one CS and switching to another
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CS or read followed by write on the same CS. Minimum value is
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actually 1, so a value of 0 will still yield 1 recovery cycle.
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minimum: 0
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maximum: 15
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qcom,xmem-write-hold-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The extra cycles inserted after every write minimum 1. The
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data out is driven from the time WE is asserted until CS is
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asserted. With a hold of 1 (value = 0), the CS stays active
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for 1 extra cycle, etc.
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minimum: 0
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maximum: 15
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qcom,xmem-write-delta-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The initial latency for write cycles inserted for the first
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write to a page or burst memory.
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minimum: 0
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maximum: 255
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qcom,xmem-read-delta-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The initial latency for read cycles inserted for the first
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read to a page or burst memory.
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minimum: 0
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maximum: 255
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qcom,xmem-write-wait-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The number of wait cycles for every write access.
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minimum: 0
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maximum: 15
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qcom,xmem-read-wait-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The number of wait cycles for every read access.
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minimum: 0
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maximum: 15
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# FAST chip selects
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qcom,xmem-address-hold-enable:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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Holds the address for an extra cycle to meet hold time
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requirements with ADV assertion, when set to 1.
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enum: [ 0, 1 ]
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qcom,xmem-adv-to-oe-recovery-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The number of cycles elapsed before an OE assertion, with
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respect to the cycle where ADV (address valid) is asserted.
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minimum: 0
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maximum: 3
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qcom,xmem-read-hold-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The length in cycles of the first segment of a read transfer.
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For a single read transfer this will be the time from CS
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assertion to OE assertion.
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minimum: 0
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maximum: 15
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required:
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-msm8660.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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external-bus@1a100000 {
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compatible = "qcom,msm8660-ebi2";
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reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
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reg-names = "ebi2", "xmem";
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ranges = <0 0x0 0x1a800000 0x00800000>,
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<1 0x0 0x1b000000 0x00800000>,
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<2 0x0 0x1b800000 0x00800000>,
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<3 0x0 0x1d000000 0x08000000>,
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<4 0x0 0x1c800000 0x00800000>,
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<5 0x0 0x1c000000 0x00800000>;
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clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
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clock-names = "ebi2x", "ebi2";
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#address-cells = <2>;
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#size-cells = <1>;
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ethernet@2,0 {
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compatible = "smsc,lan9221", "smsc,lan9115";
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reg = <2 0x0 0x100>;
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interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>,
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<&tlmm 29 IRQ_TYPE_EDGE_RISING>;
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reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
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phy-mode = "mii";
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reg-io-width = <2>;
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smsc,force-external-phy;
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smsc,irq-push-pull;
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/* SLOW chipselect config */
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qcom,xmem-recovery-cycles = <0>;
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qcom,xmem-write-hold-cycles = <3>;
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qcom,xmem-write-delta-cycles = <31>;
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qcom,xmem-read-delta-cycles = <28>;
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qcom,xmem-write-wait-cycles = <9>;
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qcom,xmem-read-wait-cycles = <9>;
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};
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};
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