446 lines
11 KiB
C
446 lines
11 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* NXP NETC Blocks Control Driver
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*
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* Copyright 2024 NXP
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*
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* This driver is used for pre-initialization of NETC, such as PCS and MII
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* protocols, LDID, warm reset, etc. Therefore, all NETC device drivers can
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* only be probed after the netc-blk-crtl driver has completed initialization.
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* In addition, when the system enters suspend mode, IERB, PRB, and NETCMIX
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* will be powered off, except for WOL. Therefore, when the system resumes,
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* these blocks need to be reinitialized.
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*/
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/fsl/netc_global.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_net.h>
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#include <linux/of_platform.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/seq_file.h>
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/* NETCMIX registers */
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#define IMX95_CFG_LINK_IO_VAR 0x0
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#define IO_VAR_16FF_16G_SERDES 0x1
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#define IO_VAR(port, var) (((var) & 0xf) << ((port) << 2))
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#define IMX95_CFG_LINK_MII_PROT 0x4
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#define CFG_LINK_MII_PORT_0 GENMASK(3, 0)
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#define CFG_LINK_MII_PORT_1 GENMASK(7, 4)
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#define MII_PROT_MII 0x0
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#define MII_PROT_RMII 0x1
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#define MII_PROT_RGMII 0x2
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#define MII_PROT_SERIAL 0x3
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#define MII_PROT(port, prot) (((prot) & 0xf) << ((port) << 2))
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#define IMX95_CFG_LINK_PCS_PROT(a) (0x8 + (a) * 4)
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#define PCS_PROT_1G_SGMII BIT(0)
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#define PCS_PROT_2500M_SGMII BIT(1)
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#define PCS_PROT_XFI BIT(3)
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#define PCS_PROT_SFI BIT(4)
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#define PCS_PROT_10G_SXGMII BIT(6)
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/* NETC privileged register block register */
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#define PRB_NETCRR 0x100
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#define NETCRR_SR BIT(0)
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#define NETCRR_LOCK BIT(1)
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#define PRB_NETCSR 0x104
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#define NETCSR_ERROR BIT(0)
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#define NETCSR_STATE BIT(1)
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/* NETC integrated endpoint register block register */
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#define IERB_EMDIOFAUXR 0x344
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#define IERB_T0FAUXR 0x444
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#define IERB_EFAUXR(a) (0x3044 + 0x100 * (a))
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#define IERB_VFAUXR(a) (0x4004 + 0x40 * (a))
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#define FAUXR_LDID GENMASK(3, 0)
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/* Platform information */
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#define IMX95_ENETC0_BUS_DEVFN 0x0
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#define IMX95_ENETC1_BUS_DEVFN 0x40
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#define IMX95_ENETC2_BUS_DEVFN 0x80
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/* Flags for different platforms */
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#define NETC_HAS_NETCMIX BIT(0)
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struct netc_devinfo {
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u32 flags;
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int (*netcmix_init)(struct platform_device *pdev);
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int (*ierb_init)(struct platform_device *pdev);
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};
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struct netc_blk_ctrl {
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void __iomem *prb;
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void __iomem *ierb;
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void __iomem *netcmix;
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const struct netc_devinfo *devinfo;
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struct platform_device *pdev;
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struct dentry *debugfs_root;
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};
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static void netc_reg_write(void __iomem *base, u32 offset, u32 val)
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{
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netc_write(base + offset, val);
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}
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static u32 netc_reg_read(void __iomem *base, u32 offset)
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{
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return netc_read(base + offset);
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}
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static int netc_of_pci_get_bus_devfn(struct device_node *np)
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{
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u32 reg[5];
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int error;
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error = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg));
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if (error)
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return error;
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return (reg[0] >> 8) & 0xffff;
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}
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static int netc_get_link_mii_protocol(phy_interface_t interface)
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{
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switch (interface) {
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case PHY_INTERFACE_MODE_MII:
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return MII_PROT_MII;
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case PHY_INTERFACE_MODE_RMII:
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return MII_PROT_RMII;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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return MII_PROT_RGMII;
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_2500BASEX:
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case PHY_INTERFACE_MODE_10GBASER:
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case PHY_INTERFACE_MODE_XGMII:
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case PHY_INTERFACE_MODE_USXGMII:
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return MII_PROT_SERIAL;
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default:
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return -EINVAL;
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}
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}
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static int imx95_netcmix_init(struct platform_device *pdev)
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{
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struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
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struct device_node *np = pdev->dev.of_node;
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phy_interface_t interface;
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int bus_devfn, mii_proto;
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u32 val;
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int err;
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/* Default setting of MII protocol */
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val = MII_PROT(0, MII_PROT_RGMII) | MII_PROT(1, MII_PROT_RGMII) |
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MII_PROT(2, MII_PROT_SERIAL);
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/* Update the link MII protocol through parsing phy-mode */
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for_each_available_child_of_node_scoped(np, child) {
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for_each_available_child_of_node_scoped(child, gchild) {
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if (!of_device_is_compatible(gchild, "pci1131,e101"))
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continue;
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bus_devfn = netc_of_pci_get_bus_devfn(gchild);
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if (bus_devfn < 0)
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return -EINVAL;
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if (bus_devfn == IMX95_ENETC2_BUS_DEVFN)
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continue;
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err = of_get_phy_mode(gchild, &interface);
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if (err)
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continue;
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mii_proto = netc_get_link_mii_protocol(interface);
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if (mii_proto < 0)
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return -EINVAL;
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switch (bus_devfn) {
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case IMX95_ENETC0_BUS_DEVFN:
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val = u32_replace_bits(val, mii_proto,
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CFG_LINK_MII_PORT_0);
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break;
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case IMX95_ENETC1_BUS_DEVFN:
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val = u32_replace_bits(val, mii_proto,
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CFG_LINK_MII_PORT_1);
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break;
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default:
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return -EINVAL;
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}
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}
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}
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/* Configure Link I/O variant */
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netc_reg_write(priv->netcmix, IMX95_CFG_LINK_IO_VAR,
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IO_VAR(2, IO_VAR_16FF_16G_SERDES));
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/* Configure Link 2 PCS protocol */
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netc_reg_write(priv->netcmix, IMX95_CFG_LINK_PCS_PROT(2),
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PCS_PROT_10G_SXGMII);
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netc_reg_write(priv->netcmix, IMX95_CFG_LINK_MII_PROT, val);
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return 0;
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}
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static bool netc_ierb_is_locked(struct netc_blk_ctrl *priv)
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{
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return !!(netc_reg_read(priv->prb, PRB_NETCRR) & NETCRR_LOCK);
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}
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static int netc_lock_ierb(struct netc_blk_ctrl *priv)
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{
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u32 val;
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netc_reg_write(priv->prb, PRB_NETCRR, NETCRR_LOCK);
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return read_poll_timeout(netc_reg_read, val, !(val & NETCSR_STATE),
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100, 2000, false, priv->prb, PRB_NETCSR);
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}
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static int netc_unlock_ierb_with_warm_reset(struct netc_blk_ctrl *priv)
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{
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u32 val;
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netc_reg_write(priv->prb, PRB_NETCRR, 0);
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return read_poll_timeout(netc_reg_read, val, !(val & NETCRR_LOCK),
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1000, 100000, true, priv->prb, PRB_NETCRR);
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}
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static int imx95_ierb_init(struct platform_device *pdev)
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{
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struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
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/* EMDIO : No MSI-X intterupt */
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netc_reg_write(priv->ierb, IERB_EMDIOFAUXR, 0);
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/* ENETC0 PF */
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netc_reg_write(priv->ierb, IERB_EFAUXR(0), 0);
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/* ENETC0 VF0 */
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netc_reg_write(priv->ierb, IERB_VFAUXR(0), 1);
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/* ENETC0 VF1 */
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netc_reg_write(priv->ierb, IERB_VFAUXR(1), 2);
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/* ENETC1 PF */
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netc_reg_write(priv->ierb, IERB_EFAUXR(1), 3);
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/* ENETC1 VF0 */
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netc_reg_write(priv->ierb, IERB_VFAUXR(2), 5);
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/* ENETC1 VF1 */
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netc_reg_write(priv->ierb, IERB_VFAUXR(3), 6);
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/* ENETC2 PF */
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netc_reg_write(priv->ierb, IERB_EFAUXR(2), 4);
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/* ENETC2 VF0 */
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netc_reg_write(priv->ierb, IERB_VFAUXR(4), 5);
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/* ENETC2 VF1 */
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netc_reg_write(priv->ierb, IERB_VFAUXR(5), 6);
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/* NETC TIMER */
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netc_reg_write(priv->ierb, IERB_T0FAUXR, 7);
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return 0;
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}
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static int netc_ierb_init(struct platform_device *pdev)
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{
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struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
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const struct netc_devinfo *devinfo = priv->devinfo;
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int err;
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if (netc_ierb_is_locked(priv)) {
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err = netc_unlock_ierb_with_warm_reset(priv);
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if (err) {
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dev_err(&pdev->dev, "Unlock IERB failed.\n");
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return err;
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}
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}
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if (devinfo->ierb_init) {
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err = devinfo->ierb_init(pdev);
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if (err)
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return err;
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}
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err = netc_lock_ierb(priv);
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if (err) {
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dev_err(&pdev->dev, "Lock IERB failed.\n");
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return err;
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}
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return 0;
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}
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#if IS_ENABLED(CONFIG_DEBUG_FS)
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static int netc_prb_show(struct seq_file *s, void *data)
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{
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struct netc_blk_ctrl *priv = s->private;
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u32 val;
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val = netc_reg_read(priv->prb, PRB_NETCRR);
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seq_printf(s, "[PRB NETCRR] Lock:%d SR:%d\n",
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(val & NETCRR_LOCK) ? 1 : 0,
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(val & NETCRR_SR) ? 1 : 0);
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val = netc_reg_read(priv->prb, PRB_NETCSR);
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seq_printf(s, "[PRB NETCSR] State:%d Error:%d\n",
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(val & NETCSR_STATE) ? 1 : 0,
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(val & NETCSR_ERROR) ? 1 : 0);
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(netc_prb);
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static void netc_blk_ctrl_create_debugfs(struct netc_blk_ctrl *priv)
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{
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struct dentry *root;
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root = debugfs_create_dir("netc_blk_ctrl", NULL);
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if (IS_ERR(root))
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return;
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priv->debugfs_root = root;
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debugfs_create_file("prb", 0444, root, priv, &netc_prb_fops);
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}
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static void netc_blk_ctrl_remove_debugfs(struct netc_blk_ctrl *priv)
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{
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debugfs_remove_recursive(priv->debugfs_root);
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priv->debugfs_root = NULL;
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}
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#else
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static void netc_blk_ctrl_create_debugfs(struct netc_blk_ctrl *priv)
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{
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}
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static void netc_blk_ctrl_remove_debugfs(struct netc_blk_ctrl *priv)
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{
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}
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#endif
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static int netc_prb_check_error(struct netc_blk_ctrl *priv)
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{
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if (netc_reg_read(priv->prb, PRB_NETCSR) & NETCSR_ERROR)
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return -1;
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return 0;
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}
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static const struct netc_devinfo imx95_devinfo = {
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.flags = NETC_HAS_NETCMIX,
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.netcmix_init = imx95_netcmix_init,
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.ierb_init = imx95_ierb_init,
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};
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static const struct of_device_id netc_blk_ctrl_match[] = {
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{ .compatible = "nxp,imx95-netc-blk-ctrl", .data = &imx95_devinfo },
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{},
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};
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MODULE_DEVICE_TABLE(of, netc_blk_ctrl_match);
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static int netc_blk_ctrl_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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const struct netc_devinfo *devinfo;
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struct device *dev = &pdev->dev;
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const struct of_device_id *id;
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struct netc_blk_ctrl *priv;
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struct clk *ipg_clk;
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void __iomem *regs;
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int err;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->pdev = pdev;
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ipg_clk = devm_clk_get_optional_enabled(dev, "ipg");
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if (IS_ERR(ipg_clk))
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return dev_err_probe(dev, PTR_ERR(ipg_clk),
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"Set ipg clock failed\n");
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id = of_match_device(netc_blk_ctrl_match, dev);
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if (!id)
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return dev_err_probe(dev, -EINVAL, "Cannot match device\n");
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devinfo = (struct netc_devinfo *)id->data;
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if (!devinfo)
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return dev_err_probe(dev, -EINVAL, "No device information\n");
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priv->devinfo = devinfo;
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regs = devm_platform_ioremap_resource_byname(pdev, "ierb");
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if (IS_ERR(regs))
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return dev_err_probe(dev, PTR_ERR(regs),
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"Missing IERB resource\n");
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priv->ierb = regs;
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regs = devm_platform_ioremap_resource_byname(pdev, "prb");
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if (IS_ERR(regs))
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return dev_err_probe(dev, PTR_ERR(regs),
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"Missing PRB resource\n");
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priv->prb = regs;
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if (devinfo->flags & NETC_HAS_NETCMIX) {
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regs = devm_platform_ioremap_resource_byname(pdev, "netcmix");
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if (IS_ERR(regs))
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return dev_err_probe(dev, PTR_ERR(regs),
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"Missing NETCMIX resource\n");
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priv->netcmix = regs;
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}
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platform_set_drvdata(pdev, priv);
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if (devinfo->netcmix_init) {
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err = devinfo->netcmix_init(pdev);
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if (err)
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return dev_err_probe(dev, err,
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"Initializing NETCMIX failed\n");
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}
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err = netc_ierb_init(pdev);
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if (err)
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return dev_err_probe(dev, err, "Initializing IERB failed\n");
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if (netc_prb_check_error(priv) < 0)
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dev_warn(dev, "The current IERB configuration is invalid\n");
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netc_blk_ctrl_create_debugfs(priv);
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err = of_platform_populate(node, NULL, NULL, dev);
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if (err) {
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netc_blk_ctrl_remove_debugfs(priv);
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return dev_err_probe(dev, err, "of_platform_populate failed\n");
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}
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return 0;
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}
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static void netc_blk_ctrl_remove(struct platform_device *pdev)
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{
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struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
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of_platform_depopulate(&pdev->dev);
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netc_blk_ctrl_remove_debugfs(priv);
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}
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static struct platform_driver netc_blk_ctrl_driver = {
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.driver = {
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.name = "nxp-netc-blk-ctrl",
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.of_match_table = netc_blk_ctrl_match,
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},
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.probe = netc_blk_ctrl_probe,
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.remove = netc_blk_ctrl_remove,
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};
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module_platform_driver(netc_blk_ctrl_driver);
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MODULE_DESCRIPTION("NXP NETC Blocks Control Driver");
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MODULE_LICENSE("Dual BSD/GPL");
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