258 lines
7.9 KiB
C
258 lines
7.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __BCMASP_INTF_DEFS_H
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#define __BCMASP_INTF_DEFS_H
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#define UMC_OFFSET(intf) \
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((((intf)->port) * 0x800) + 0xc000)
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#define UMC_CMD 0x008
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#define UMC_CMD_TX_EN BIT(0)
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#define UMC_CMD_RX_EN BIT(1)
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#define UMC_CMD_SPEED_SHIFT 0x2
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#define UMC_CMD_SPEED_MASK 0x3
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#define UMC_CMD_SPEED_10 0x0
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#define UMC_CMD_SPEED_100 0x1
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#define UMC_CMD_SPEED_1000 0x2
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#define UMC_CMD_SPEED_2500 0x3
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#define UMC_CMD_PROMISC BIT(4)
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#define UMC_CMD_PAD_EN BIT(5)
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#define UMC_CMD_CRC_FWD BIT(6)
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#define UMC_CMD_PAUSE_FWD BIT(7)
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#define UMC_CMD_RX_PAUSE_IGNORE BIT(8)
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#define UMC_CMD_TX_ADDR_INS BIT(9)
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#define UMC_CMD_HD_EN BIT(10)
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#define UMC_CMD_SW_RESET BIT(13)
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#define UMC_CMD_LCL_LOOP_EN BIT(15)
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#define UMC_CMD_AUTO_CONFIG BIT(22)
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#define UMC_CMD_CNTL_FRM_EN BIT(23)
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#define UMC_CMD_NO_LEN_CHK BIT(24)
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#define UMC_CMD_RMT_LOOP_EN BIT(25)
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#define UMC_CMD_PRBL_EN BIT(27)
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#define UMC_CMD_TX_PAUSE_IGNORE BIT(28)
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#define UMC_CMD_TX_RX_EN BIT(29)
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#define UMC_CMD_RUNT_FILTER_DIS BIT(30)
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#define UMC_MAC0 0x0c
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#define UMC_MAC1 0x10
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#define UMC_FRM_LEN 0x14
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#define UMC_EEE_CTRL 0x64
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#define EN_LPI_RX_PAUSE BIT(0)
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#define EN_LPI_TX_PFC BIT(1)
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#define EN_LPI_TX_PAUSE BIT(2)
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#define EEE_EN BIT(3)
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#define RX_FIFO_CHECK BIT(4)
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#define EEE_TX_CLK_DIS BIT(5)
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#define DIS_EEE_10M BIT(6)
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#define LP_IDLE_PREDICTION_MODE BIT(7)
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#define UMC_EEE_LPI_TIMER 0x68
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#define UMC_PAUSE_CNTRL 0x330
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#define UMC_TX_FLUSH 0x334
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#define UMC_GR64 0x400
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#define UMC_GR127 0x404
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#define UMC_GR255 0x408
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#define UMC_GR511 0x40c
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#define UMC_GR1023 0x410
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#define UMC_GR1518 0x414
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#define UMC_GRMGV 0x418
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#define UMC_GR2047 0x41c
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#define UMC_GR4095 0x420
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#define UMC_GR9216 0x424
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#define UMC_GRPKT 0x428
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#define UMC_GRBYT 0x42c
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#define UMC_GRMCA 0x430
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#define UMC_GRBCA 0x434
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#define UMC_GRFCS 0x438
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#define UMC_GRXCF 0x43c
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#define UMC_GRXPF 0x440
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#define UMC_GRXUO 0x444
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#define UMC_GRALN 0x448
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#define UMC_GRFLR 0x44c
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#define UMC_GRCDE 0x450
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#define UMC_GRFCR 0x454
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#define UMC_GROVR 0x458
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#define UMC_GRJBR 0x45c
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#define UMC_GRMTUE 0x460
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#define UMC_GRPOK 0x464
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#define UMC_GRUC 0x468
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#define UMC_GRPPP 0x46c
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#define UMC_GRMCRC 0x470
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#define UMC_TR64 0x480
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#define UMC_TR127 0x484
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#define UMC_TR255 0x488
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#define UMC_TR511 0x48c
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#define UMC_TR1023 0x490
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#define UMC_TR1518 0x494
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#define UMC_TRMGV 0x498
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#define UMC_TR2047 0x49c
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#define UMC_TR4095 0x4a0
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#define UMC_TR9216 0x4a4
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#define UMC_GTPKT 0x4a8
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#define UMC_GTMCA 0x4ac
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#define UMC_GTBCA 0x4b0
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#define UMC_GTXPF 0x4b4
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#define UMC_GTXCF 0x4b8
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#define UMC_GTFCS 0x4bc
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#define UMC_GTOVR 0x4c0
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#define UMC_GTDRF 0x4c4
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#define UMC_GTEDF 0x4c8
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#define UMC_GTSCL 0x4cc
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#define UMC_GTMCL 0x4d0
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#define UMC_GTLCL 0x4d4
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#define UMC_GTXCL 0x4d8
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#define UMC_GTFRG 0x4dc
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#define UMC_GTNCL 0x4e0
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#define UMC_GTJBR 0x4e4
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#define UMC_GTBYT 0x4e8
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#define UMC_GTPOK 0x4ec
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#define UMC_GTUC 0x4f0
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#define UMC_RRPKT 0x500
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#define UMC_RRUND 0x504
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#define UMC_RRFRG 0x508
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#define UMC_RRBYT 0x50c
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#define UMC_MIB_CNTRL 0x580
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#define UMC_MIB_CNTRL_RX_CNT_RST BIT(0)
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#define UMC_MIB_CNTRL_RUNT_CNT_RST BIT(1)
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#define UMC_MIB_CNTRL_TX_CNT_RST BIT(2)
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#define UMC_RX_MAX_PKT_SZ 0x608
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#define UMC_MPD_CTRL 0x620
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#define UMC_MPD_CTRL_MPD_EN BIT(0)
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#define UMC_MPD_CTRL_PSW_EN BIT(27)
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#define UMC_PSW_MS 0x624
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#define UMC_PSW_LS 0x628
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#define UMAC2FB_OFFSET_2_1 0x9f044
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#define UMAC2FB_OFFSET 0x9f03c
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#define UMAC2FB_CFG 0x0
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#define UMAC2FB_CFG_OPUT_EN BIT(0)
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#define UMAC2FB_CFG_VLAN_EN BIT(1)
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#define UMAC2FB_CFG_SNAP_EN BIT(2)
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#define UMAC2FB_CFG_BCM_TG_EN BIT(3)
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#define UMAC2FB_CFG_IPUT_EN BIT(4)
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#define UMAC2FB_CFG_CHID_SHIFT 8
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#define UMAC2FB_CFG_OK_SEND_SHIFT 24
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#define UMAC2FB_CFG_DEFAULT_EN \
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(UMAC2FB_CFG_OPUT_EN | UMAC2FB_CFG_VLAN_EN \
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| UMAC2FB_CFG_SNAP_EN | UMAC2FB_CFG_IPUT_EN)
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#define RGMII_OFFSET(intf) \
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((((intf)->port) * 0x100) + 0xd000)
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#define RGMII_EPHY_CNTRL 0x00
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#define RGMII_EPHY_CFG_IDDQ_BIAS BIT(0)
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#define RGMII_EPHY_CFG_EXT_PWRDOWN BIT(1)
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#define RGMII_EPHY_CFG_FORCE_DLL_EN BIT(2)
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#define RGMII_EPHY_CFG_IDDQ_GLOBAL BIT(3)
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#define RGMII_EPHY_CK25_DIS BIT(4)
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#define RGMII_EPHY_RESET BIT(7)
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#define RGMII_OOB_CNTRL 0x0c
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#define RGMII_LINK BIT(4)
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#define RGMII_OOB_DIS BIT(5)
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#define RGMII_MODE_EN BIT(6)
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#define RGMII_ID_MODE_DIS BIT(16)
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#define RGMII_PORT_CNTRL 0x60
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#define RGMII_PORT_MODE_EPHY 0
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#define RGMII_PORT_MODE_GPHY 1
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#define RGMII_PORT_MODE_EXT_EPHY 2
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#define RGMII_PORT_MODE_EXT_GPHY 3
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#define RGMII_PORT_MODE_EXT_RVMII 4
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#define RGMII_PORT_MODE_MASK GENMASK(2, 0)
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#define RGMII_SYS_LED_CNTRL 0x74
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#define RGMII_SYS_LED_CNTRL_LINK_OVRD BIT(15)
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#define TX_SPB_DMA_OFFSET(intf) \
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((((intf)->channel) * 0x30) + 0x48180)
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#define TX_SPB_DMA_READ 0x00
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#define TX_SPB_DMA_BASE 0x08
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#define TX_SPB_DMA_END 0x10
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#define TX_SPB_DMA_VALID 0x18
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#define TX_SPB_DMA_FIFO_CTRL 0x20
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#define TX_SPB_DMA_FIFO_FLUSH BIT(0)
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#define TX_SPB_DMA_FIFO_STATUS 0x24
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#define TX_SPB_CTRL_OFFSET(intf) \
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((((intf)->channel) * 0x68) + 0x49340)
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#define TX_SPB_CTRL_ENABLE 0x0
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#define TX_SPB_CTRL_ENABLE_EN BIT(0)
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#define TX_SPB_CTRL_XF_CTRL2 0x20
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#define TX_SPB_CTRL_XF_BID_SHIFT 16
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#define TX_SPB_TOP_OFFSET(intf) \
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((((intf)->channel) * 0x1c) + 0x4a0e0)
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#define TX_SPB_TOP_BLKOUT 0x0
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#define TX_SPB_TOP_SPRE_BW_CTRL 0x4
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#define TX_EPKT_C_OFFSET(intf) \
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((((intf)->channel) * 0x120) + 0x40900)
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#define TX_EPKT_C_CFG_MISC 0x0
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#define TX_EPKT_C_CFG_MISC_EN BIT(0)
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#define TX_EPKT_C_CFG_MISC_PT BIT(1)
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#define TX_EPKT_C_CFG_MISC_PS_SHIFT 14
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#define TX_EPKT_C_CFG_MISC_FD_SHIFT 20
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#define TX_PAUSE_CTRL_OFFSET(intf) \
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((((intf)->channel * 0xc) + 0x49a20))
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#define TX_PAUSE_MAP_VECTOR 0x8
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#define RX_EDPKT_DMA_OFFSET(intf) \
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((((intf)->channel) * 0x38) + 0x9ca00)
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#define RX_EDPKT_DMA_WRITE 0x00
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#define RX_EDPKT_DMA_READ 0x08
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#define RX_EDPKT_DMA_BASE 0x10
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#define RX_EDPKT_DMA_END 0x18
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#define RX_EDPKT_DMA_VALID 0x20
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#define RX_EDPKT_DMA_FULLNESS 0x28
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#define RX_EDPKT_DMA_MIN_THRES 0x2c
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#define RX_EDPKT_DMA_CH_XONOFF 0x30
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#define RX_EDPKT_CFG_OFFSET(intf) \
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((((intf)->channel) * 0x70) + 0x9c600)
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#define RX_EDPKT_CFG_CFG0 0x0
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#define RX_EDPKT_CFG_CFG0_DBUF_SHIFT 9
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#define RX_EDPKT_CFG_CFG0_RBUF 0x0
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#define RX_EDPKT_CFG_CFG0_RBUF_4K 0x1
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#define RX_EDPKT_CFG_CFG0_BUF_4K 0x2
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/* EFRM STUFF, 0 = no byte stuff, 1 = two byte stuff */
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#define RX_EDPKT_CFG_CFG0_EFRM_STUF BIT(11)
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#define RX_EDPKT_CFG_CFG0_BALN_SHIFT 12
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#define RX_EDPKT_CFG_CFG0_NO_ALN 0
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#define RX_EDPKT_CFG_CFG0_4_ALN 2
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#define RX_EDPKT_CFG_CFG0_64_ALN 6
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#define RX_EDPKT_RING_BUFFER_WRITE 0x38
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#define RX_EDPKT_RING_BUFFER_READ 0x40
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#define RX_EDPKT_RING_BUFFER_BASE 0x48
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#define RX_EDPKT_RING_BUFFER_END 0x50
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#define RX_EDPKT_RING_BUFFER_VALID 0x58
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#define RX_EDPKT_CFG_ENABLE 0x6c
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#define RX_EDPKT_CFG_ENABLE_EN BIT(0)
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#define RX_SPB_DMA_OFFSET(intf) \
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((((intf)->channel) * 0x30) + 0xa0000)
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#define RX_SPB_DMA_READ 0x00
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#define RX_SPB_DMA_BASE 0x08
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#define RX_SPB_DMA_END 0x10
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#define RX_SPB_DMA_VALID 0x18
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#define RX_SPB_DMA_FIFO_CTRL 0x20
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#define RX_SPB_DMA_FIFO_FLUSH BIT(0)
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#define RX_SPB_DMA_FIFO_STATUS 0x24
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#define RX_SPB_CTRL_OFFSET(intf) \
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((((intf)->channel - 6) * 0x68) + 0xa1000)
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#define RX_SPB_CTRL_ENABLE 0x00
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#define RX_SPB_CTRL_ENABLE_EN BIT(0)
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#define RX_PAUSE_CTRL_OFFSET(intf) \
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((((intf)->channel - 6) * 0x4) + 0xa1138)
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#define RX_PAUSE_MAP_VECTOR 0x00
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#define RX_SPB_TOP_CTRL_OFFSET(intf) \
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((((intf)->channel - 6) * 0x14) + 0xa2000)
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#define RX_SPB_TOP_BLKOUT 0x00
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#define NUM_4K_BUFFERS 32
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#define RING_BUFFER_SIZE (PAGE_SIZE * NUM_4K_BUFFERS)
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#define DESC_RING_COUNT (64 * NUM_4K_BUFFERS)
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#define DESC_SIZE 16
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#define DESC_RING_SIZE (DESC_RING_COUNT * DESC_SIZE)
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#endif
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