229 lines
8.6 KiB
C
229 lines
8.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* AD3552R Digital <-> Analog converters common header
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*
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* Copyright 2021-2024 Analog Devices Inc.
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* Author: Angelo Dureghello <adureghello@baylibre.com>
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*/
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#ifndef __DRIVERS_IIO_DAC_AD3552R_H__
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#define __DRIVERS_IIO_DAC_AD3552R_H__
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/* Register addresses */
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/* Primary address space */
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#define AD3552R_REG_ADDR_INTERFACE_CONFIG_A 0x00
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#define AD3552R_MASK_SOFTWARE_RESET (BIT(7) | BIT(0))
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#define AD3552R_MASK_ADDR_ASCENSION BIT(5)
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#define AD3552R_MASK_SDO_ACTIVE BIT(4)
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#define AD3552R_REG_ADDR_INTERFACE_CONFIG_B 0x01
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#define AD3552R_MASK_SINGLE_INST BIT(7)
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#define AD3552R_MASK_SHORT_INSTRUCTION BIT(3)
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#define AD3552R_REG_ADDR_DEVICE_CONFIG 0x02
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#define AD3552R_MASK_DEVICE_STATUS(n) BIT(4 + (n))
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#define AD3552R_MASK_CUSTOM_MODES GENMASK(3, 2)
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#define AD3552R_MASK_OPERATING_MODES GENMASK(1, 0)
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#define AD3552R_REG_ADDR_CHIP_TYPE 0x03
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#define AD3552R_MASK_CLASS GENMASK(7, 0)
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#define AD3552R_REG_ADDR_PRODUCT_ID_L 0x04
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#define AD3552R_REG_ADDR_PRODUCT_ID_H 0x05
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#define AD3552R_REG_ADDR_CHIP_GRADE 0x06
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#define AD3552R_MASK_GRADE GENMASK(7, 4)
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#define AD3552R_MASK_DEVICE_REVISION GENMASK(3, 0)
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#define AD3552R_REG_ADDR_SCRATCH_PAD 0x0A
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#define AD3552R_REG_ADDR_SPI_REVISION 0x0B
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#define AD3552R_REG_ADDR_VENDOR_L 0x0C
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#define AD3552R_REG_ADDR_VENDOR_H 0x0D
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#define AD3552R_REG_ADDR_STREAM_MODE 0x0E
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#define AD3552R_MASK_LENGTH GENMASK(7, 0)
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#define AD3552R_REG_ADDR_TRANSFER_REGISTER 0x0F
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#define AD3552R_MASK_MULTI_IO_MODE GENMASK(7, 6)
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#define AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE BIT(2)
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#define AD3552R_REG_ADDR_INTERFACE_CONFIG_C 0x10
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#define AD3552R_MASK_CRC_ENABLE \
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(GENMASK(7, 6) | GENMASK(1, 0))
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#define AD3552R_MASK_STRICT_REGISTER_ACCESS BIT(5)
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#define AD3552R_REG_ADDR_INTERFACE_STATUS_A 0x11
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#define AD3552R_MASK_INTERFACE_NOT_READY BIT(7)
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#define AD3552R_MASK_CLOCK_COUNTING_ERROR BIT(5)
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#define AD3552R_MASK_INVALID_OR_NO_CRC BIT(3)
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#define AD3552R_MASK_WRITE_TO_READ_ONLY_REGISTER BIT(2)
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#define AD3552R_MASK_PARTIAL_REGISTER_ACCESS BIT(1)
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#define AD3552R_MASK_REGISTER_ADDRESS_INVALID BIT(0)
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#define AD3552R_REG_ADDR_INTERFACE_CONFIG_D 0x14
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#define AD3552R_MASK_ALERT_ENABLE_PULLUP BIT(6)
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#define AD3552R_MASK_MEM_CRC_EN BIT(4)
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#define AD3552R_MASK_SDO_DRIVE_STRENGTH GENMASK(3, 2)
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#define AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN BIT(1)
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#define AD3552R_MASK_SPI_CONFIG_DDR BIT(0)
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#define AD3552R_REG_ADDR_SH_REFERENCE_CONFIG 0x15
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#define AD3552R_MASK_IDUMP_FAST_MODE BIT(6)
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#define AD3552R_MASK_SAMPLE_HOLD_DIFF_USER_EN BIT(5)
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#define AD3552R_MASK_SAMPLE_HOLD_USER_TRIM GENMASK(4, 3)
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#define AD3552R_MASK_SAMPLE_HOLD_USER_ENABLE BIT(2)
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#define AD3552R_MASK_REFERENCE_VOLTAGE_SEL GENMASK(1, 0)
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#define AD3552R_REG_ADDR_ERR_ALARM_MASK 0x16
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#define AD3552R_MASK_REF_RANGE_ALARM BIT(6)
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#define AD3552R_MASK_CLOCK_COUNT_ERR_ALARM BIT(5)
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#define AD3552R_MASK_MEM_CRC_ERR_ALARM BIT(4)
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#define AD3552R_MASK_SPI_CRC_ERR_ALARM BIT(3)
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#define AD3552R_MASK_WRITE_TO_READ_ONLY_ALARM BIT(2)
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#define AD3552R_MASK_PARTIAL_REGISTER_ACCESS_ALARM BIT(1)
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#define AD3552R_MASK_REGISTER_ADDRESS_INVALID_ALARM BIT(0)
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#define AD3552R_REG_ADDR_ERR_STATUS 0x17
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#define AD3552R_MASK_REF_RANGE_ERR_STATUS BIT(6)
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#define AD3552R_MASK_STREAM_EXCEEDS_DAC_ERR_STATUS BIT(5)
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#define AD3552R_MASK_MEM_CRC_ERR_STATUS BIT(4)
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#define AD3552R_MASK_RESET_STATUS BIT(0)
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#define AD3552R_REG_ADDR_POWERDOWN_CONFIG 0x18
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#define AD3552R_MASK_CH_DAC_POWERDOWN(ch) BIT(4 + (ch))
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#define AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch) BIT(ch)
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#define AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE 0x19
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#define AD3552R_MASK_CH0_RANGE GENMASK(2, 0)
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#define AD3552R_MASK_CH1_RANGE GENMASK(6, 4)
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#define AD3552R_MASK_CH_OUTPUT_RANGE GENMASK(7, 0)
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#define AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch) \
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((ch) ? GENMASK(7, 4) : GENMASK(3, 0))
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#define AD3552R_REG_ADDR_CH_OFFSET(ch) (0x1B + (ch) * 2)
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#define AD3552R_MASK_CH_OFFSET_BITS_0_7 GENMASK(7, 0)
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#define AD3552R_REG_ADDR_CH_GAIN(ch) (0x1C + (ch) * 2)
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#define AD3552R_MASK_CH_RANGE_OVERRIDE BIT(7)
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#define AD3552R_MASK_CH_GAIN_SCALING_N GENMASK(6, 5)
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#define AD3552R_MASK_CH_GAIN_SCALING_P GENMASK(4, 3)
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#define AD3552R_MASK_CH_OFFSET_POLARITY BIT(2)
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#define AD3552R_MASK_CH_OFFSET_BIT_8 BIT(8)
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/*
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* Secondary region
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* For multibyte registers specify the highest address because the access is
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* done in descending order
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*/
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#define AD3552R_SECONDARY_REGION_START 0x28
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#define AD3552R_REG_ADDR_HW_LDAC_16B 0x28
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#define AD3552R_REG_ADDR_CH_DAC_16B(ch) (0x2C - (1 - (ch)) * 2)
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#define AD3552R_REG_ADDR_DAC_PAGE_MASK_16B 0x2E
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#define AD3552R_REG_ADDR_CH_SELECT_16B 0x2F
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#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_16B 0x31
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#define AD3552R_REG_ADDR_SW_LDAC_16B 0x32
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#define AD3552R_REG_ADDR_CH_INPUT_16B(ch) (0x36 - (1 - (ch)) * 2)
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/* 3 bytes registers */
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#define AD3552R_REG_START_24B 0x37
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#define AD3552R_REG_ADDR_HW_LDAC_24B 0x37
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#define AD3552R_REG_ADDR_CH_DAC_24B(ch) (0x3D - (1 - (ch)) * 3)
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#define AD3552R_REG_ADDR_DAC_PAGE_MASK_24B 0x40
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#define AD3552R_REG_ADDR_CH_SELECT_24B 0x41
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#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B 0x44
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#define AD3552R_REG_ADDR_SW_LDAC_24B 0x45
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#define AD3552R_REG_ADDR_CH_INPUT_24B(ch) (0x4B - (1 - (ch)) * 3)
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#define AD3552R_MAX_CH 2
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#define AD3552R_MASK_CH(ch) BIT(ch)
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#define AD3552R_MASK_ALL_CH GENMASK(1, 0)
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#define AD3552R_MAX_REG_SIZE 3
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#define AD3552R_READ_BIT BIT(7)
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#define AD3552R_ADDR_MASK GENMASK(6, 0)
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#define AD3552R_MASK_DAC_12B GENMASK(15, 4)
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#define AD3552R_DEFAULT_CONFIG_B_VALUE 0x8
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#define AD3552R_SCRATCH_PAD_TEST_VAL1 0x34
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#define AD3552R_SCRATCH_PAD_TEST_VAL2 0xB2
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#define AD3552R_GAIN_SCALE 1000
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#define AD3552R_LDAC_PULSE_US 100
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#define AD3552R_CH0_ACTIVE BIT(0)
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#define AD3552R_CH1_ACTIVE BIT(1)
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#define AD3552R_MAX_RANGES 5
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#define AD3542R_MAX_RANGES 6
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#define AD3552R_QUAD_SPI 2
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extern const s32 ad3552r_ch_ranges[AD3552R_MAX_RANGES][2];
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extern const s32 ad3542r_ch_ranges[AD3542R_MAX_RANGES][2];
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enum ad3552r_id {
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AD3541R_ID = 0x400b,
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AD3542R_ID = 0x4009,
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AD3551R_ID = 0x400a,
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AD3552R_ID = 0x4008,
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};
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struct ad3552r_model_data {
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const char *model_name;
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enum ad3552r_id chip_id;
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unsigned int num_hw_channels;
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const s32 (*ranges_table)[2];
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int num_ranges;
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bool requires_output_range;
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};
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struct ad3552r_ch_data {
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s32 scale_int;
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s32 scale_dec;
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s32 offset_int;
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s32 offset_dec;
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s16 gain_offset;
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u16 rfb;
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u8 n;
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u8 p;
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u8 range;
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bool range_override;
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};
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enum ad3552r_ch_gain_scaling {
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/* Gain scaling of 1 */
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AD3552R_CH_GAIN_SCALING_1,
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/* Gain scaling of 0.5 */
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AD3552R_CH_GAIN_SCALING_0_5,
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/* Gain scaling of 0.25 */
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AD3552R_CH_GAIN_SCALING_0_25,
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/* Gain scaling of 0.125 */
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AD3552R_CH_GAIN_SCALING_0_125,
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};
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enum ad3552r_ch_vref_select {
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/* Internal source with Vref I/O floating */
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AD3552R_INTERNAL_VREF_PIN_FLOATING,
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/* Internal source with Vref I/O at 2.5V */
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AD3552R_INTERNAL_VREF_PIN_2P5V,
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/* External source with Vref I/O as input */
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AD3552R_EXTERNAL_VREF_PIN_INPUT
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};
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enum ad3542r_ch_output_range {
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/* Range from 0 V to 2.5 V. Requires Rfb1x connection */
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AD3542R_CH_OUTPUT_RANGE_0__2P5V,
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/* Range from 0 V to 3 V. Requires Rfb1x connection */
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AD3542R_CH_OUTPUT_RANGE_0__3V,
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/* Range from 0 V to 5 V. Requires Rfb1x connection */
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AD3542R_CH_OUTPUT_RANGE_0__5V,
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/* Range from 0 V to 10 V. Requires Rfb2x connection */
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AD3542R_CH_OUTPUT_RANGE_0__10V,
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/* Range from -2.5 V to 7.5 V. Requires Rfb2x connection */
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AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V,
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/* Range from -5 V to 5 V. Requires Rfb2x connection */
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AD3542R_CH_OUTPUT_RANGE_NEG_5__5V,
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};
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enum ad3552r_ch_output_range {
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/* Range from 0 V to 2.5 V. Requires Rfb1x connection */
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AD3552R_CH_OUTPUT_RANGE_0__2P5V,
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/* Range from 0 V to 5 V. Requires Rfb1x connection */
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AD3552R_CH_OUTPUT_RANGE_0__5V,
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/* Range from 0 V to 10 V. Requires Rfb2x connection */
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AD3552R_CH_OUTPUT_RANGE_0__10V,
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/* Range from -5 V to 5 V. Requires Rfb2x connection */
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AD3552R_CH_OUTPUT_RANGE_NEG_5__5V,
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/* Range from -10 V to 10 V. Requires Rfb4x connection */
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AD3552R_CH_OUTPUT_RANGE_NEG_10__10V,
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};
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int ad3552r_get_output_range(struct device *dev,
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const struct ad3552r_model_data *model_info,
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struct fwnode_handle *child, u32 *val);
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int ad3552r_get_custom_gain(struct device *dev, struct fwnode_handle *child,
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u8 *gs_p, u8 *gs_n, u16 *rfb, s16 *goffs);
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u16 ad3552r_calc_custom_gain(u8 p, u8 n, s16 goffs);
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int ad3552r_get_ref_voltage(struct device *dev, u32 *val);
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int ad3552r_get_drive_strength(struct device *dev, u32 *val);
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void ad3552r_calc_gain_and_offset(struct ad3552r_ch_data *ch_data,
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const struct ad3552r_model_data *model_data);
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#endif /* __DRIVERS_IIO_DAC_AD3552R_H__ */
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