177 lines
4.5 KiB
YAML
177 lines
4.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/fsl,imx-asrc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Asynchronous Sample Rate Converter (ASRC) Controller
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description:
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The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of
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a signal associated with an input clock into a signal associated with a
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different output clock. The driver currently works as a Front End of DPCM
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with other Back Ends Audio controller such as ESAI, SSI and SAI. It has
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three pairs to support three substreams within totally 10 channels.
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maintainers:
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- Shawn Guo <shawnguo@kernel.org>
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- Sascha Hauer <s.hauer@pengutronix.de>
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,imx35-asrc
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- fsl,imx53-asrc
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- fsl,imx8qm-asrc
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- fsl,imx8qxp-asrc
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- items:
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- enum:
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- fsl,imx6sx-asrc
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- fsl,imx6ul-asrc
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- const: fsl,imx53-asrc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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dmas:
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maxItems: 6
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dma-names:
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items:
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- const: rxa
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- const: rxb
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- const: rxc
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- const: txa
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- const: txb
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- const: txc
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clocks:
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maxItems: 19
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clock-names:
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items:
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- const: mem
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- const: ipg
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- const: asrck_0
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- const: asrck_1
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- const: asrck_2
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- const: asrck_3
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- const: asrck_4
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- const: asrck_5
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- const: asrck_6
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- const: asrck_7
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- const: asrck_8
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- const: asrck_9
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- const: asrck_a
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- const: asrck_b
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- const: asrck_c
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- const: asrck_d
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- const: asrck_e
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- const: asrck_f
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- const: spba
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power-domains:
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maxItems: 1
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fsl,asrc-rate:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: The mutual sample rate used by DPCM Back Ends
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fsl,asrc-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: The mutual sample width used by DPCM Back Ends
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enum: [16, 24]
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fsl,asrc-clk-map:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Defines clock map used in driver
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<0> - select the map for asrc0 in imx8qm/imx8qxp
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<1> - select the map for asrc1 in imx8qm/imx8qxp
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enum: [0, 1]
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big-endian:
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type: boolean
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description:
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If this property is absent, the little endian mode will be in use as
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default. Otherwise, the big endian mode will be in use for all the
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device registers.
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fsl,asrc-format:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Defines a mutual sample format used by DPCM Back Ends, which can
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replace the fsl,asrc-width. The value is 2 (S16_LE), or 6 (S24_LE).
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enum: [2, 6]
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required:
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- compatible
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- reg
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- interrupts
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- dmas
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- dma-names
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- clocks
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- clock-names
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- fsl,asrc-rate
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- fsl,asrc-width
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qm-asrc
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- fsl,imx8qxp-asrc
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then:
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required:
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- fsl,asrc-clk-map
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else:
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properties:
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fsl,asrc-clk-map: false
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qm-asrc
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- fsl,imx8qxp-asrc
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then:
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required:
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/imx6qdl-clock.h>
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asrc: asrc@2034000 {
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compatible = "fsl,imx53-asrc";
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reg = <0x02034000 0x4000>;
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interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
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<&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
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<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
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<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
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<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
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<&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
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<&clks IMX6QDL_CLK_SPBA>;
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clock-names = "mem", "ipg", "asrck_0",
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"asrck_1", "asrck_2", "asrck_3", "asrck_4",
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"asrck_5", "asrck_6", "asrck_7", "asrck_8",
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"asrck_9", "asrck_a", "asrck_b", "asrck_c",
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"asrck_d", "asrck_e", "asrck_f", "spba";
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dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
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<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
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dma-names = "rxa", "rxb", "rxc",
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"txa", "txb", "txc";
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fsl,asrc-rate = <48000>;
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fsl,asrc-width = <16>;
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};
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