103 lines
2.2 KiB
YAML
103 lines
2.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/bridge/fsl,imx8mp-hdmi-tx.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8MP DWC HDMI TX Encoder
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maintainers:
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- Lucas Stach <l.stach@pengutronix.de>
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description:
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The i.MX8MP HDMI transmitter is a Synopsys DesignWare
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HDMI 2.0a TX controller IP.
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allOf:
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- $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml#
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properties:
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compatible:
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enum:
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- fsl,imx8mp-hdmi-tx
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reg-io-width:
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const: 1
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: iahb
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- const: isfr
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- const: cec
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- const: pix
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power-domains:
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: Parallel RGB input port
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: HDMI output port
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- power-domains
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- ports
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mp-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/imx8mp-power.h>
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hdmi@32fd8000 {
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compatible = "fsl,imx8mp-hdmi-tx";
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reg = <0x32fd8000 0x7eff>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MP_CLK_HDMI_APB>,
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<&clk IMX8MP_CLK_HDMI_REF_266M>,
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<&clk IMX8MP_CLK_32K>,
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<&hdmi_tx_phy>;
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clock-names = "iahb", "isfr", "cec", "pix";
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power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
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reg-io-width = <1>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hdmi_tx_from_pvi: endpoint {
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remote-endpoint = <&pvi_to_hdmi_tx>;
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};
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};
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port@1 {
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reg = <1>;
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hdmi_tx_out: endpoint {
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remote-endpoint = <&hdmi0_con>;
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};
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};
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};
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};
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