108 lines
2.2 KiB
YAML
108 lines
2.2 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/actions,owl-timer.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Actions Semi Owl timer
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maintainers:
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- Andreas Färber <afaerber@suse.de>
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description:
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Actions Semi Owl SoCs provide 32bit and 2Hz timers.
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The 32bit timers support dynamic irq, as well as one-shot mode.
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properties:
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compatible:
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enum:
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- actions,s500-timer
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- actions,s700-timer
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- actions,s900-timer
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clocks:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 6
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interrupt-names:
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minItems: 1
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maxItems: 6
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items:
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enum:
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- 2hz0
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- 2hz1
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- timer0
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- timer1
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- timer2
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- timer3
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reg:
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maxItems: 1
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required:
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- compatible
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- clocks
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- interrupts
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- interrupt-names
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- reg
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- actions,s500-timer
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then:
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properties:
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interrupts:
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minItems: 4
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maxItems: 4
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interrupt-names:
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items:
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- const: 2hz0
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- const: 2hz1
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- const: timer0
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- const: timer1
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- if:
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properties:
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compatible:
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contains:
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enum:
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- actions,s700-timer
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- actions,s900-timer
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then:
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properties:
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interrupts:
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minItems: 1
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maxItems: 1
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interrupt-names:
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items:
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- const: timer1
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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timer@b0168000 {
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compatible = "actions,s500-timer";
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reg = <0xb0168000 0x100>;
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clocks = <&hosc>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "2hz0", "2hz1", "timer0", "timer1";
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};
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};
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...
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