178 lines
5.2 KiB
JSON
178 lines
5.2 KiB
JSON
|
[
|
||
|
{
|
||
|
"EventName": "l3_lookup_state.l3_miss",
|
||
|
"EventCode": "0x04",
|
||
|
"BriefDescription": "L3 cache misses.",
|
||
|
"UMask": "0x01",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_lookup_state.l3_hit",
|
||
|
"EventCode": "0x04",
|
||
|
"BriefDescription": "L3 cache hits.",
|
||
|
"UMask": "0xfe",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_lookup_state.all_coherent_accesses_to_l3",
|
||
|
"EventCode": "0x04",
|
||
|
"BriefDescription": "L3 cache requests for all coherent accesses.",
|
||
|
"UMask": "0xff",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_xi_sampled_latency.dram_near",
|
||
|
"EventCode": "0xac",
|
||
|
"BriefDescription": "Average sampled latency when data is sourced from DRAM in the same NUMA node.",
|
||
|
"UMask": "0x01",
|
||
|
"EnAllCores": "0x1",
|
||
|
"EnAllSlices": "0x1",
|
||
|
"SliceId": "0x3",
|
||
|
"ThreadMask": "0x3",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_xi_sampled_latency.dram_far",
|
||
|
"EventCode": "0xac",
|
||
|
"BriefDescription": "Average sampled latency when data is sourced from DRAM in a different NUMA node.",
|
||
|
"UMask": "0x02",
|
||
|
"EnAllCores": "0x1",
|
||
|
"EnAllSlices": "0x1",
|
||
|
"SliceId": "0x3",
|
||
|
"ThreadMask": "0x3",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_xi_sampled_latency.near_cache",
|
||
|
"EventCode": "0xac",
|
||
|
"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node.",
|
||
|
"UMask": "0x04",
|
||
|
"EnAllCores": "0x1",
|
||
|
"EnAllSlices": "0x1",
|
||
|
"SliceId": "0x3",
|
||
|
"ThreadMask": "0x3",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_xi_sampled_latency.far_cache",
|
||
|
"EventCode": "0xac",
|
||
|
"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node.",
|
||
|
"UMask": "0x08",
|
||
|
"EnAllCores": "0x1",
|
||
|
"EnAllSlices": "0x1",
|
||
|
"SliceId": "0x3",
|
||
|
"ThreadMask": "0x3",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_xi_sampled_latency.ext_near",
|
||
|
"EventCode": "0xac",
|
||
|
"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node.",
|
||
|
"UMask": "0x10",
|
||
|
"EnAllCores": "0x1",
|
||
|
"EnAllSlices": "0x1",
|
||
|
"SliceId": "0x3",
|
||
|
"ThreadMask": "0x3",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_xi_sampled_latency.ext_far",
|
||
|
"EventCode": "0xac",
|
||
|
"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node.",
|
||
|
"UMask": "0x20",
|
||
|
"EnAllCores": "0x1",
|
||
|
"EnAllSlices": "0x1",
|
||
|
"SliceId": "0x3",
|
||
|
"ThreadMask": "0x3",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_xi_sampled_latency.all",
|
||
|
"EventCode": "0xac",
|
||
|
"BriefDescription": "Average sampled latency from all data sources.",
|
||
|
"UMask": "0x3f",
|
||
|
"EnAllCores": "0x1",
|
||
|
"EnAllSlices": "0x1",
|
||
|
"SliceId": "0x3",
|
||
|
"ThreadMask": "0x3",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_xi_sampled_latency_requests.dram_near",
|
||
|
"EventCode": "0xad",
|
||
|
"BriefDescription": "L3 cache fill requests sourced from DRAM in the same NUMA node.",
|
||
|
"UMask": "0x01",
|
||
|
"EnAllCores": "0x1",
|
||
|
"EnAllSlices": "0x1",
|
||
|
"SliceId": "0x3",
|
||
|
"ThreadMask": "0x3",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_xi_sampled_latency_requests.dram_far",
|
||
|
"EventCode": "0xad",
|
||
|
"BriefDescription": "L3 cache fill requests sourced from DRAM in a different NUMA node.",
|
||
|
"UMask": "0x02",
|
||
|
"EnAllCores": "0x1",
|
||
|
"EnAllSlices": "0x1",
|
||
|
"SliceId": "0x3",
|
||
|
"ThreadMask": "0x3",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_xi_sampled_latency_requests.near_cache",
|
||
|
"EventCode": "0xad",
|
||
|
"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node.",
|
||
|
"UMask": "0x04",
|
||
|
"EnAllCores": "0x1",
|
||
|
"EnAllSlices": "0x1",
|
||
|
"SliceId": "0x3",
|
||
|
"ThreadMask": "0x3",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_xi_sampled_latency_requests.far_cache",
|
||
|
"EventCode": "0xad",
|
||
|
"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node.",
|
||
|
"UMask": "0x08",
|
||
|
"EnAllCores": "0x1",
|
||
|
"EnAllSlices": "0x1",
|
||
|
"SliceId": "0x3",
|
||
|
"ThreadMask": "0x3",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_xi_sampled_latency_requests.ext_near",
|
||
|
"EventCode": "0xad",
|
||
|
"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node.",
|
||
|
"UMask": "0x10",
|
||
|
"EnAllCores": "0x1",
|
||
|
"EnAllSlices": "0x1",
|
||
|
"SliceId": "0x3",
|
||
|
"ThreadMask": "0x3",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_xi_sampled_latency_requests.ext_far",
|
||
|
"EventCode": "0xad",
|
||
|
"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node.",
|
||
|
"UMask": "0x20",
|
||
|
"EnAllCores": "0x1",
|
||
|
"EnAllSlices": "0x1",
|
||
|
"SliceId": "0x3",
|
||
|
"ThreadMask": "0x3",
|
||
|
"Unit": "L3PMC"
|
||
|
},
|
||
|
{
|
||
|
"EventName": "l3_xi_sampled_latency_requests.all",
|
||
|
"EventCode": "0xad",
|
||
|
"BriefDescription": "L3 cache fill requests sourced from all data sources.",
|
||
|
"UMask": "0x3f",
|
||
|
"EnAllCores": "0x1",
|
||
|
"EnAllSlices": "0x1",
|
||
|
"SliceId": "0x3",
|
||
|
"ThreadMask": "0x3",
|
||
|
"Unit": "L3PMC"
|
||
|
}
|
||
|
]
|