209 lines
5.6 KiB
JSON
209 lines
5.6 KiB
JSON
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[
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{
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"ArchStdEvent": "L1D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WR"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_RD"
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},
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{
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"ArchStdEvent": "L1D_CACHE_INVAL",
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"Errata": "Errata AC04_CPU_1",
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"BriefDescription": "L1D cache invalidate. Impacted by errata -"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL_RD"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_RD"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL_RD"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL_WR"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_VICTIM"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB_CLEAN"
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},
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{
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"ArchStdEvent": "L2D_CACHE_INVAL"
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},
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{
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"ArchStdEvent": "L1I_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1I_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1I_CACHE"
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},
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{
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"ArchStdEvent": "L2D_CACHE"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB"
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},
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{
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"ArchStdEvent": "L1D_TLB"
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},
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{
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"ArchStdEvent": "L1I_TLB"
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},
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{
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"ArchStdEvent": "L2D_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L2I_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L2D_TLB"
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},
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{
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"ArchStdEvent": "L2I_TLB"
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},
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{
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"ArchStdEvent": "DTLB_WALK"
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},
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{
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"ArchStdEvent": "ITLB_WALK"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL_WR"
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},
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{
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"ArchStdEvent": "L1D_CACHE_LMISS_RD"
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},
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{
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"ArchStdEvent": "L1I_CACHE_LMISS"
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},
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{
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"ArchStdEvent": "L2D_CACHE_LMISS_RD"
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},
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{
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"PublicDescription": "Level 1 data or unified cache demand access",
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"EventCode": "0x8140",
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"EventName": "L1D_CACHE_RW",
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"BriefDescription": "Level 1 data or unified cache demand access"
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},
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{
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"PublicDescription": "Level 1 data or unified cache preload or prefetch",
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"EventCode": "0x8142",
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"EventName": "L1D_CACHE_PRFM",
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"BriefDescription": "Level 1 data or unified cache preload or prefetch"
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},
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{
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"PublicDescription": "Level 1 data or unified cache refill, preload or prefetch",
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"EventCode": "0x8146",
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"EventName": "L1D_CACHE_REFILL_PRFM",
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"BriefDescription": "Level 1 data or unified cache refill, preload or prefetch"
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},
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{
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"ArchStdEvent": "L1D_TLB_RD"
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},
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{
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"ArchStdEvent": "L1D_TLB_WR"
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},
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{
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"ArchStdEvent": "L2D_TLB_REFILL_RD"
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},
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{
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"ArchStdEvent": "L2D_TLB_REFILL_WR"
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},
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{
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"ArchStdEvent": "L2D_TLB_RD"
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},
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{
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"ArchStdEvent": "L2D_TLB_WR"
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},
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{
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"PublicDescription": "L1D TLB miss",
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"EventCode": "0xD600",
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"EventName": "L1D_TLB_MISS",
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"BriefDescription": "L1D TLB miss"
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},
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{
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"PublicDescription": "Level 1 prefetcher, load prefetch requests generated",
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"EventCode": "0xd606",
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"EventName": "L1_PREFETCH_LD_GEN",
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"BriefDescription": "Level 1 prefetcher, load prefetch requests generated"
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},
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{
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"PublicDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache",
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"EventCode": "0xd607",
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"EventName": "L1_PREFETCH_LD_FILL",
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"BriefDescription": "Level 1 prefetcher, load prefetch fills into the level 1 cache"
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},
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{
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"PublicDescription": "Level 1 prefetcher, load prefetch to level 2 generated",
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"EventCode": "0xd608",
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"EventName": "L1_PREFETCH_L2_REQ",
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"BriefDescription": "Level 1 prefetcher, load prefetch to level 2 generated"
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},
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{
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"PublicDescription": "L1 prefetcher, distance was reset",
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"EventCode": "0xd609",
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"EventName": "L1_PREFETCH_DIST_RST",
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"BriefDescription": "L1 prefetcher, distance was reset"
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},
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{
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"PublicDescription": "L1 prefetcher, distance was increased",
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"EventCode": "0xd60a",
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"EventName": "L1_PREFETCH_DIST_INC",
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"BriefDescription": "L1 prefetcher, distance was increased"
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},
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{
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"PublicDescription": "Level 1 prefetcher, table entry is trained",
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"EventCode": "0xd60b",
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"EventName": "L1_PREFETCH_ENTRY_TRAINED",
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"BriefDescription": "Level 1 prefetcher, table entry is trained"
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},
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{
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"PublicDescription": "L1 data cache refill - Read or Write",
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"EventCode": "0xd60e",
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"EventName": "L1D_CACHE_REFILL_RW",
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"BriefDescription": "L1 data cache refill - Read or Write"
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},
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{
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"PublicDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills",
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"EventCode": "0xD701",
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"EventName": "L2C_INST_REFILL",
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"BriefDescription": "Level 2 cache refill from instruction-side miss, including IMMU refills"
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},
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{
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"PublicDescription": "Level 2 cache refill from data-side miss, including DMMU refills",
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"EventCode": "0xD702",
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"EventName": "L2C_DATA_REFILL",
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"BriefDescription": "Level 2 cache refill from data-side miss, including DMMU refills"
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},
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{
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"PublicDescription": "Level 2 cache prefetcher, load prefetch requests generated",
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"EventCode": "0xD703",
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"EventName": "L2_PREFETCH_REQ",
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"BriefDescription": "Level 2 cache prefetcher, load prefetch requests generated"
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}
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]
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