103 lines
2.6 KiB
Plaintext
103 lines
2.6 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include "stm32mp131.dtsi"
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/ {
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soc {
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m_can1: can@4400e000 {
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compatible = "bosch,m_can";
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reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
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clock-names = "hclk", "cclk";
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bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
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status = "disabled";
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};
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m_can2: can@4400f000 {
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compatible = "bosch,m_can";
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reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
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clock-names = "hclk", "cclk";
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bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
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status = "disabled";
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};
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};
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};
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&etzpc {
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adc_1: adc@48003000 {
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compatible = "st,stm32mp13-adc-core";
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reg = <0x48003000 0x400>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc ADC1>, <&rcc ADC1_K>;
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clock-names = "bus", "adc";
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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access-controllers = <&etzpc 32>;
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status = "disabled";
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adc1: adc@0 {
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compatible = "st,stm32mp13-adc";
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#io-channel-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>;
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interrupt-parent = <&adc_1>;
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interrupts = <0>;
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dmas = <&dmamux1 9 0x400 0x80000001>;
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dma-names = "rx";
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status = "disabled";
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channel@18 {
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reg = <18>;
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label = "vrefint";
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};
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};
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};
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ethernet2: ethernet@5800e000 {
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compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
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reg = <0x5800e000 0x2000>;
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reg-names = "stmmaceth";
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interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clock-names = "stmmaceth",
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"mac-clk-tx",
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"mac-clk-rx",
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"ethstp",
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"eth-ck";
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clocks = <&rcc ETH2MAC>,
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<&rcc ETH2TX>,
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<&rcc ETH2RX>,
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<&rcc ETH2STP>,
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<&rcc ETH2CK_K>;
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st,syscon = <&syscfg 0x4 0xff000000>;
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snps,mixed-burst;
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snps,pbl = <2>;
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snps,axi-config = <&stmmac_axi_config_2>;
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snps,tso;
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access-controllers = <&etzpc 49>;
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status = "disabled";
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stmmac_axi_config_2: stmmac-axi-config {
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snps,blen = <0 0 0 0 16 8 4>;
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snps,rd_osr_lmt = <0x7>;
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snps,wr_osr_lmt = <0x7>;
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};
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};
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};
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