77 lines
2.7 KiB
C
77 lines
2.7 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H
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#define _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H
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#define NSS_CC_SWITCH_CORE_ARES 1
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#define NSS_CC_APB_BRIDGE_ARES 2
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#define NSS_CC_MAC0_TX_ARES 3
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#define NSS_CC_MAC0_TX_SRDS1_ARES 4
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#define NSS_CC_MAC0_RX_ARES 5
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#define NSS_CC_MAC0_RX_SRDS1_ARES 6
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#define NSS_CC_MAC1_SRDS1_CH0_RX_ARES 7
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#define NSS_CC_MAC1_TX_ARES 8
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#define NSS_CC_MAC1_GEPHY0_TX_ARES 9
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#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_ARES 10
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#define NSS_CC_MAC1_SRDS1_CH0_TX_ARES 11
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#define NSS_CC_MAC1_RX_ARES 12
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#define NSS_CC_MAC1_GEPHY0_RX_ARES 13
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#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_ARES 14
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#define NSS_CC_MAC2_SRDS1_CH1_RX_ARES 15
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#define NSS_CC_MAC2_TX_ARES 16
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#define NSS_CC_MAC2_GEPHY1_TX_ARES 17
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#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_ARES 18
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#define NSS_CC_MAC2_SRDS1_CH1_TX_ARES 19
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#define NSS_CC_MAC2_RX_ARES 20
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#define NSS_CC_MAC2_GEPHY1_RX_ARES 21
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#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_ARES 22
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#define NSS_CC_MAC3_SRDS1_CH2_RX_ARES 23
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#define NSS_CC_MAC3_TX_ARES 24
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#define NSS_CC_MAC3_GEPHY2_TX_ARES 25
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#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_ARES 26
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#define NSS_CC_MAC3_SRDS1_CH2_TX_ARES 27
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#define NSS_CC_MAC3_RX_ARES 28
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#define NSS_CC_MAC3_GEPHY2_RX_ARES 29
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#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_ARES 30
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#define NSS_CC_MAC4_SRDS1_CH3_RX_ARES 31
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#define NSS_CC_MAC4_TX_ARES 32
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#define NSS_CC_MAC4_GEPHY3_TX_ARES 33
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#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_ARES 34
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#define NSS_CC_MAC4_SRDS1_CH3_TX_ARES 35
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#define NSS_CC_MAC4_RX_ARES 36
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#define NSS_CC_MAC4_GEPHY3_RX_ARES 37
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#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_ARES 38
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#define NSS_CC_MAC5_TX_ARES 39
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#define NSS_CC_MAC5_TX_SRDS0_ARES 40
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#define NSS_CC_MAC5_RX_ARES 41
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#define NSS_CC_MAC5_RX_SRDS0_ARES 42
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#define NSS_CC_AHB_ARES 43
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#define NSS_CC_SEC_CTRL_AHB_ARES 44
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#define NSS_CC_TLMM_ARES 45
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#define NSS_CC_TLMM_AHB_ARES 46
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#define NSS_CC_CNOC_AHB_ARES 47
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#define NSS_CC_MDIO_AHB_ARES 48
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#define NSS_CC_MDIO_MASTER_AHB_ARES 49
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#define NSS_CC_SRDS0_SYS_ARES 50
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#define NSS_CC_SRDS1_SYS_ARES 51
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#define NSS_CC_GEPHY0_SYS_ARES 52
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#define NSS_CC_GEPHY1_SYS_ARES 53
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#define NSS_CC_GEPHY2_SYS_ARES 54
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#define NSS_CC_GEPHY3_SYS_ARES 55
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#define NSS_CC_SEC_CTRL_ARES 56
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#define NSS_CC_SEC_CTRL_SENSE_ARES 57
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#define NSS_CC_SLEEP_ARES 58
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#define NSS_CC_DEBUG_ARES 59
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#define NSS_CC_GEPHY0_ARES 60
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#define NSS_CC_GEPHY1_ARES 61
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#define NSS_CC_GEPHY2_ARES 62
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#define NSS_CC_GEPHY3_ARES 63
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#define NSS_CC_DSP_ARES 64
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#define NSS_CC_GEPHY_FULL_ARES 65
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#define NSS_CC_GLOBAL_ARES 66
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#define NSS_CC_XPCS_ARES 67
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#endif
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