120 lines
2.8 KiB
C
120 lines
2.8 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (c) 2023 Amlogic, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_AMLOGIC_C3_RESET_H
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#define _DT_BINDINGS_AMLOGIC_C3_RESET_H
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/* RESET0 */
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/* 0-3 */
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#define RESET_USBCTRL 4
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/* 5-7 */
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#define RESET_USBPHY20 8
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/* 9 */
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#define RESET_USB2DRD 10
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#define RESET_MIPI_DSI_HOST 11
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#define RESET_MIPI_DSI_PHY 12
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/* 13-20 */
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#define RESET_GE2D 21
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#define RESET_DWAP 22
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/* 23-31 */
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/* RESET1 */
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#define RESET_AUDIO 32
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/* 33-34 */
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#define RESET_DDRAPB 35
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#define RESET_DDR 36
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#define RESET_DOS_CAPB3 37
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#define RESET_DOS 38
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/* 39-46 */
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#define RESET_NNA 47
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#define RESET_ETHERNET 48
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#define RESET_ISP 49
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#define RESET_VC9000E_APB 50
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#define RESET_VC9000E_A 51
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/* 52 */
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#define RESET_VC9000E_CORE 53
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/* 54-63 */
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/* RESET2 */
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#define RESET_ABUS_ARB 64
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#define RESET_IRCTRL 65
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/* 66 */
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#define RESET_TEMP_PII 67
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/* 68-72 */
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#define RESET_SPICC_0 73
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#define RESET_SPICC_1 74
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#define RESET_RSA 75
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/* 76-79 */
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#define RESET_MSR_CLK 80
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#define RESET_SPIFC 81
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#define RESET_SAR_ADC 82
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/* 83-87 */
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#define RESET_ACODEC 88
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/* 89-90 */
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#define RESET_WATCHDOG 91
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/* 92-95 */
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/* RESET3 */
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#define RESET_ISP_NIC_GPV 96
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#define RESET_ISP_NIC_MAIN 97
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#define RESET_ISP_NIC_VCLK 98
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#define RESET_ISP_NIC_VOUT 99
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#define RESET_ISP_NIC_ALL 100
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#define RESET_VOUT 101
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#define RESET_VOUT_VENC 102
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/* 103 */
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#define RESET_CVE_NIC_GPV 104
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#define RESET_CVE_NIC_MAIN 105
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#define RESET_CVE_NIC_GE2D 106
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#define RESET_CVE_NIC_DW 106
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#define RESET_CVE_NIC_CVE 108
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#define RESET_CVE_NIC_ALL 109
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#define RESET_CVE 110
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/* 112-127 */
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/* RESET4 */
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#define RESET_RTC 128
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#define RESET_PWM_AB 129
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#define RESET_PWM_CD 130
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#define RESET_PWM_EF 131
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#define RESET_PWM_GH 132
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#define RESET_PWM_IJ 133
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#define RESET_PWM_KL 134
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#define RESET_PWM_MN 135
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/* 136-137 */
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#define RESET_UART_A 138
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#define RESET_UART_B 139
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#define RESET_UART_C 140
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#define RESET_UART_D 141
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#define RESET_UART_E 142
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#define RESET_UART_F 143
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#define RESET_I2C_S_A 144
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#define RESET_I2C_M_A 145
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#define RESET_I2C_M_B 146
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#define RESET_I2C_M_C 147
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#define RESET_I2C_M_D 148
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/* 149-151 */
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#define RESET_SD_EMMC_A 152
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#define RESET_SD_EMMC_B 153
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#define RESET_SD_EMMC_C 154
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/* RESET5 */
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/* 160-172 */
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#define RESET_BRG_NIC_NNA 173
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#define RESET_BRG_MUX_NIC_MAIN 174
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#define RESET_BRG_AO_NIC_ALL 175
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/* 176-183 */
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#define RESET_BRG_NIC_VAPB 184
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#define RESET_BRG_NIC_SDIO_B 185
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#define RESET_BRG_NIC_SDIO_A 186
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#define RESET_BRG_NIC_EMMC 187
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#define RESET_BRG_NIC_DSU 188
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#define RESET_BRG_NIC_SYSCLK 189
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#define RESET_BRG_NIC_MAIN 190
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#define RESET_BRG_NIC_ALL 191
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#endif
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