513 lines
13 KiB
C
513 lines
13 KiB
C
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "xe_ring_ops.h"
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#include <generated/xe_wa_oob.h>
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#include "instructions/xe_gpu_commands.h"
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#include "instructions/xe_mi_commands.h"
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#include "regs/xe_engine_regs.h"
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#include "regs/xe_gt_regs.h"
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#include "regs/xe_lrc_layout.h"
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#include "xe_exec_queue_types.h"
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#include "xe_gt.h"
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#include "xe_lrc.h"
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#include "xe_macros.h"
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#include "xe_sched_job.h"
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#include "xe_sriov.h"
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#include "xe_vm_types.h"
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#include "xe_vm.h"
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#include "xe_wa.h"
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/*
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* 3D-related flags that can't be set on _engines_ that lack access to the 3D
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* pipeline (i.e., CCS engines).
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*/
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#define PIPE_CONTROL_3D_ENGINE_FLAGS (\
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PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | \
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PIPE_CONTROL_DEPTH_CACHE_FLUSH | \
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PIPE_CONTROL_TILE_CACHE_FLUSH | \
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PIPE_CONTROL_DEPTH_STALL | \
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PIPE_CONTROL_STALL_AT_SCOREBOARD | \
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PIPE_CONTROL_PSD_SYNC | \
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PIPE_CONTROL_AMFS_FLUSH | \
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PIPE_CONTROL_VF_CACHE_INVALIDATE | \
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PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET)
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/* 3D-related flags that can't be set on _platforms_ that lack a 3D pipeline */
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#define PIPE_CONTROL_3D_ARCH_FLAGS ( \
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PIPE_CONTROL_3D_ENGINE_FLAGS | \
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PIPE_CONTROL_INDIRECT_STATE_DISABLE | \
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PIPE_CONTROL_FLUSH_ENABLE | \
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PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
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PIPE_CONTROL_DC_FLUSH_ENABLE)
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static u32 preparser_disable(bool state)
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{
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return MI_ARB_CHECK | BIT(8) | state;
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}
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static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg,
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u32 *dw, int i)
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{
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dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_MMIO_REMAP_EN;
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dw[i++] = reg.addr + gt->mmio.adj_offset;
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dw[i++] = AUX_INV;
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dw[i++] = MI_NOOP;
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return i;
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}
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static int emit_user_interrupt(u32 *dw, int i)
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{
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dw[i++] = MI_USER_INTERRUPT;
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dw[i++] = MI_ARB_ON_OFF | MI_ARB_ENABLE;
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dw[i++] = MI_ARB_CHECK;
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return i;
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}
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static int emit_store_imm_ggtt(u32 addr, u32 value, u32 *dw, int i)
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{
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dw[i++] = MI_STORE_DATA_IMM | MI_SDI_GGTT | MI_SDI_NUM_DW(1);
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dw[i++] = addr;
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dw[i++] = 0;
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dw[i++] = value;
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return i;
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}
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static int emit_flush_dw(u32 *dw, int i)
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{
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dw[i++] = MI_FLUSH_DW | MI_FLUSH_IMM_DW;
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dw[i++] = 0;
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dw[i++] = 0;
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dw[i++] = 0;
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return i;
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}
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static int emit_flush_imm_ggtt(u32 addr, u32 value, bool invalidate_tlb,
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u32 *dw, int i)
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{
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dw[i++] = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW |
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(invalidate_tlb ? MI_INVALIDATE_TLB : 0);
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dw[i++] = addr | MI_FLUSH_DW_USE_GTT;
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dw[i++] = 0;
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dw[i++] = value;
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return i;
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}
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static int emit_bb_start(u64 batch_addr, u32 ppgtt_flag, u32 *dw, int i)
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{
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dw[i++] = MI_BATCH_BUFFER_START | ppgtt_flag | XE_INSTR_NUM_DW(3);
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dw[i++] = lower_32_bits(batch_addr);
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dw[i++] = upper_32_bits(batch_addr);
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return i;
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}
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static int emit_flush_invalidate(u32 flag, u32 *dw, int i)
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{
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dw[i] = MI_FLUSH_DW;
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dw[i] |= flag;
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dw[i++] |= MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW |
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MI_FLUSH_DW_STORE_INDEX;
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dw[i++] = LRC_PPHWSP_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
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dw[i++] = 0;
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dw[i++] = ~0U;
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return i;
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}
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static int
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emit_pipe_control(u32 *dw, int i, u32 bit_group_0, u32 bit_group_1, u32 offset, u32 value)
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{
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dw[i++] = GFX_OP_PIPE_CONTROL(6) | bit_group_0;
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dw[i++] = bit_group_1;
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dw[i++] = offset;
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dw[i++] = 0;
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dw[i++] = value;
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dw[i++] = 0;
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return i;
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}
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static int emit_pipe_invalidate(u32 mask_flags, bool invalidate_tlb, u32 *dw,
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int i)
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{
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u32 flags = PIPE_CONTROL_CS_STALL |
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PIPE_CONTROL_COMMAND_CACHE_INVALIDATE |
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PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE |
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PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
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PIPE_CONTROL_VF_CACHE_INVALIDATE |
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PIPE_CONTROL_CONST_CACHE_INVALIDATE |
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PIPE_CONTROL_STATE_CACHE_INVALIDATE |
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PIPE_CONTROL_QW_WRITE |
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PIPE_CONTROL_STORE_DATA_INDEX;
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if (invalidate_tlb)
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flags |= PIPE_CONTROL_TLB_INVALIDATE;
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flags &= ~mask_flags;
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return emit_pipe_control(dw, i, 0, flags, LRC_PPHWSP_SCRATCH_ADDR, 0);
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}
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static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
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u32 *dw, int i)
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{
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dw[i++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(1);
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dw[i++] = lower_32_bits(addr);
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dw[i++] = upper_32_bits(addr);
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dw[i++] = lower_32_bits(value);
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dw[i++] = upper_32_bits(value);
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return i;
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}
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static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
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{
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struct xe_gt *gt = job->q->gt;
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bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
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u32 flags;
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flags = (PIPE_CONTROL_CS_STALL |
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PIPE_CONTROL_TILE_CACHE_FLUSH |
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PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
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PIPE_CONTROL_DEPTH_CACHE_FLUSH |
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PIPE_CONTROL_DC_FLUSH_ENABLE |
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PIPE_CONTROL_FLUSH_ENABLE);
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if (XE_WA(gt, 1409600907))
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flags |= PIPE_CONTROL_DEPTH_STALL;
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if (lacks_render)
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flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
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else if (job->q->class == XE_ENGINE_CLASS_COMPUTE)
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flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
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return emit_pipe_control(dw, i, PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags, 0, 0);
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}
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static int emit_pipe_control_to_ring_end(struct xe_hw_engine *hwe, u32 *dw, int i)
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{
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if (hwe->class != XE_ENGINE_CLASS_RENDER)
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return i;
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if (XE_WA(hwe->gt, 16020292621))
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i = emit_pipe_control(dw, i, 0, PIPE_CONTROL_LRI_POST_SYNC,
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RING_NOPID(hwe->mmio_base).addr, 0);
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return i;
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}
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static int emit_pipe_imm_ggtt(u32 addr, u32 value, bool stall_only, u32 *dw,
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int i)
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{
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u32 flags = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_GLOBAL_GTT_IVB |
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PIPE_CONTROL_QW_WRITE;
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if (!stall_only)
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flags |= PIPE_CONTROL_FLUSH_ENABLE;
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return emit_pipe_control(dw, i, 0, flags, addr, value);
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}
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static u32 get_ppgtt_flag(struct xe_sched_job *job)
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{
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if (job->q->vm && !job->ggtt)
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return BIT(8);
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return 0;
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}
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static int emit_copy_timestamp(struct xe_lrc *lrc, u32 *dw, int i)
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{
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dw[i++] = MI_COPY_MEM_MEM | MI_COPY_MEM_MEM_SRC_GGTT |
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MI_COPY_MEM_MEM_DST_GGTT;
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dw[i++] = xe_lrc_ctx_job_timestamp_ggtt_addr(lrc);
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dw[i++] = 0;
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dw[i++] = xe_lrc_ctx_timestamp_ggtt_addr(lrc);
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dw[i++] = 0;
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dw[i++] = MI_NOOP;
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return i;
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}
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/* for engines that don't require any special HW handling (no EUs, no aux inval, etc) */
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static void __emit_job_gen12_simple(struct xe_sched_job *job, struct xe_lrc *lrc,
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u64 batch_addr, u32 seqno)
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{
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u32 dw[MAX_JOB_SIZE_DW], i = 0;
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u32 ppgtt_flag = get_ppgtt_flag(job);
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struct xe_gt *gt = job->q->gt;
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i = emit_copy_timestamp(lrc, dw, i);
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if (job->ring_ops_flush_tlb) {
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dw[i++] = preparser_disable(true);
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i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
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seqno, true, dw, i);
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dw[i++] = preparser_disable(false);
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} else {
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i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
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seqno, dw, i);
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}
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i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
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if (job->user_fence.used) {
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i = emit_flush_dw(dw, i);
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i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
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job->user_fence.value,
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dw, i);
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}
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i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i);
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i = emit_user_interrupt(dw, i);
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xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW);
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xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
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}
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static bool has_aux_ccs(struct xe_device *xe)
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{
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/*
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* PVC is a special case that has no compression of either type
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* (FlatCCS or AuxCCS). Also, AuxCCS is no longer used from Xe2
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* onward, so any future platforms with no FlatCCS will not have
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* AuxCCS either.
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*/
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if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC)
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return false;
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return !xe->info.has_flat_ccs;
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}
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static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
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u64 batch_addr, u32 seqno)
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{
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u32 dw[MAX_JOB_SIZE_DW], i = 0;
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u32 ppgtt_flag = get_ppgtt_flag(job);
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struct xe_gt *gt = job->q->gt;
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struct xe_device *xe = gt_to_xe(gt);
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bool decode = job->q->class == XE_ENGINE_CLASS_VIDEO_DECODE;
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i = emit_copy_timestamp(lrc, dw, i);
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dw[i++] = preparser_disable(true);
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/* hsdes: 1809175790 */
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if (has_aux_ccs(xe)) {
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if (decode)
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i = emit_aux_table_inv(gt, VD0_AUX_INV, dw, i);
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else
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i = emit_aux_table_inv(gt, VE0_AUX_INV, dw, i);
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}
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if (job->ring_ops_flush_tlb)
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i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
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seqno, true, dw, i);
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dw[i++] = preparser_disable(false);
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if (!job->ring_ops_flush_tlb)
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i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
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seqno, dw, i);
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i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
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if (job->user_fence.used) {
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i = emit_flush_dw(dw, i);
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i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
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job->user_fence.value,
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dw, i);
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}
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i = emit_flush_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, false, dw, i);
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i = emit_user_interrupt(dw, i);
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xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW);
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xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
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}
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static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
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struct xe_lrc *lrc,
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u64 batch_addr, u32 seqno)
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{
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u32 dw[MAX_JOB_SIZE_DW], i = 0;
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u32 ppgtt_flag = get_ppgtt_flag(job);
|
||
|
|
struct xe_gt *gt = job->q->gt;
|
||
|
|
struct xe_device *xe = gt_to_xe(gt);
|
||
|
|
bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
|
||
|
|
u32 mask_flags = 0;
|
||
|
|
|
||
|
|
i = emit_copy_timestamp(lrc, dw, i);
|
||
|
|
|
||
|
|
dw[i++] = preparser_disable(true);
|
||
|
|
if (lacks_render)
|
||
|
|
mask_flags = PIPE_CONTROL_3D_ARCH_FLAGS;
|
||
|
|
else if (job->q->class == XE_ENGINE_CLASS_COMPUTE)
|
||
|
|
mask_flags = PIPE_CONTROL_3D_ENGINE_FLAGS;
|
||
|
|
|
||
|
|
/* See __xe_pt_bind_vma() for a discussion on TLB invalidations. */
|
||
|
|
i = emit_pipe_invalidate(mask_flags, job->ring_ops_flush_tlb, dw, i);
|
||
|
|
|
||
|
|
/* hsdes: 1809175790 */
|
||
|
|
if (has_aux_ccs(xe))
|
||
|
|
i = emit_aux_table_inv(gt, CCS_AUX_INV, dw, i);
|
||
|
|
|
||
|
|
dw[i++] = preparser_disable(false);
|
||
|
|
|
||
|
|
i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
|
||
|
|
seqno, dw, i);
|
||
|
|
|
||
|
|
i = emit_bb_start(batch_addr, ppgtt_flag, dw, i);
|
||
|
|
|
||
|
|
i = emit_render_cache_flush(job, dw, i);
|
||
|
|
|
||
|
|
if (job->user_fence.used)
|
||
|
|
i = emit_store_imm_ppgtt_posted(job->user_fence.addr,
|
||
|
|
job->user_fence.value,
|
||
|
|
dw, i);
|
||
|
|
|
||
|
|
i = emit_pipe_imm_ggtt(xe_lrc_seqno_ggtt_addr(lrc), seqno, lacks_render, dw, i);
|
||
|
|
|
||
|
|
i = emit_user_interrupt(dw, i);
|
||
|
|
|
||
|
|
i = emit_pipe_control_to_ring_end(job->q->hwe, dw, i);
|
||
|
|
|
||
|
|
xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW);
|
||
|
|
|
||
|
|
xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
|
||
|
|
}
|
||
|
|
|
||
|
|
static void emit_migration_job_gen12(struct xe_sched_job *job,
|
||
|
|
struct xe_lrc *lrc, u32 seqno)
|
||
|
|
{
|
||
|
|
u32 dw[MAX_JOB_SIZE_DW], i = 0;
|
||
|
|
|
||
|
|
i = emit_copy_timestamp(lrc, dw, i);
|
||
|
|
|
||
|
|
i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
|
||
|
|
seqno, dw, i);
|
||
|
|
|
||
|
|
dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE; /* Enabled again below */
|
||
|
|
|
||
|
|
i = emit_bb_start(job->ptrs[0].batch_addr, BIT(8), dw, i);
|
||
|
|
|
||
|
|
if (!IS_SRIOV_VF(gt_to_xe(job->q->gt))) {
|
||
|
|
/* XXX: Do we need this? Leaving for now. */
|
||
|
|
dw[i++] = preparser_disable(true);
|
||
|
|
i = emit_flush_invalidate(0, dw, i);
|
||
|
|
dw[i++] = preparser_disable(false);
|
||
|
|
}
|
||
|
|
|
||
|
|
i = emit_bb_start(job->ptrs[1].batch_addr, BIT(8), dw, i);
|
||
|
|
|
||
|
|
dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | job->migrate_flush_flags |
|
||
|
|
MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_IMM_DW;
|
||
|
|
dw[i++] = xe_lrc_seqno_ggtt_addr(lrc) | MI_FLUSH_DW_USE_GTT;
|
||
|
|
dw[i++] = 0;
|
||
|
|
dw[i++] = seqno; /* value */
|
||
|
|
|
||
|
|
i = emit_user_interrupt(dw, i);
|
||
|
|
|
||
|
|
xe_gt_assert(job->q->gt, i <= MAX_JOB_SIZE_DW);
|
||
|
|
|
||
|
|
xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
|
||
|
|
}
|
||
|
|
|
||
|
|
static void emit_job_gen12_gsc(struct xe_sched_job *job)
|
||
|
|
{
|
||
|
|
struct xe_gt *gt = job->q->gt;
|
||
|
|
|
||
|
|
xe_gt_assert(gt, job->q->width <= 1); /* no parallel submission for GSCCS */
|
||
|
|
|
||
|
|
__emit_job_gen12_simple(job, job->q->lrc[0],
|
||
|
|
job->ptrs[0].batch_addr,
|
||
|
|
xe_sched_job_lrc_seqno(job));
|
||
|
|
}
|
||
|
|
|
||
|
|
static void emit_job_gen12_copy(struct xe_sched_job *job)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
if (xe_sched_job_is_migration(job->q)) {
|
||
|
|
emit_migration_job_gen12(job, job->q->lrc[0],
|
||
|
|
xe_sched_job_lrc_seqno(job));
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0; i < job->q->width; ++i)
|
||
|
|
__emit_job_gen12_simple(job, job->q->lrc[i],
|
||
|
|
job->ptrs[i].batch_addr,
|
||
|
|
xe_sched_job_lrc_seqno(job));
|
||
|
|
}
|
||
|
|
|
||
|
|
static void emit_job_gen12_video(struct xe_sched_job *job)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
/* FIXME: Not doing parallel handshake for now */
|
||
|
|
for (i = 0; i < job->q->width; ++i)
|
||
|
|
__emit_job_gen12_video(job, job->q->lrc[i],
|
||
|
|
job->ptrs[i].batch_addr,
|
||
|
|
xe_sched_job_lrc_seqno(job));
|
||
|
|
}
|
||
|
|
|
||
|
|
static void emit_job_gen12_render_compute(struct xe_sched_job *job)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
for (i = 0; i < job->q->width; ++i)
|
||
|
|
__emit_job_gen12_render_compute(job, job->q->lrc[i],
|
||
|
|
job->ptrs[i].batch_addr,
|
||
|
|
xe_sched_job_lrc_seqno(job));
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct xe_ring_ops ring_ops_gen12_gsc = {
|
||
|
|
.emit_job = emit_job_gen12_gsc,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct xe_ring_ops ring_ops_gen12_copy = {
|
||
|
|
.emit_job = emit_job_gen12_copy,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct xe_ring_ops ring_ops_gen12_video = {
|
||
|
|
.emit_job = emit_job_gen12_video,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct xe_ring_ops ring_ops_gen12_render_compute = {
|
||
|
|
.emit_job = emit_job_gen12_render_compute,
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct xe_ring_ops *
|
||
|
|
xe_ring_ops_get(struct xe_gt *gt, enum xe_engine_class class)
|
||
|
|
{
|
||
|
|
switch (class) {
|
||
|
|
case XE_ENGINE_CLASS_OTHER:
|
||
|
|
return &ring_ops_gen12_gsc;
|
||
|
|
case XE_ENGINE_CLASS_COPY:
|
||
|
|
return &ring_ops_gen12_copy;
|
||
|
|
case XE_ENGINE_CLASS_VIDEO_DECODE:
|
||
|
|
case XE_ENGINE_CLASS_VIDEO_ENHANCE:
|
||
|
|
return &ring_ops_gen12_video;
|
||
|
|
case XE_ENGINE_CLASS_RENDER:
|
||
|
|
case XE_ENGINE_CLASS_COMPUTE:
|
||
|
|
return &ring_ops_gen12_render_compute;
|
||
|
|
default:
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
}
|