676 lines
17 KiB
C
676 lines
17 KiB
C
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/*
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* Copyright 2014 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "dp.h"
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#include "conn.h"
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#include "head.h"
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#include "ior.h"
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#include <drm/display/drm_dp.h>
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#include <subdev/bios.h>
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#include <subdev/bios/init.h>
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#include <subdev/gpio.h>
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#include <subdev/i2c.h>
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#include <nvif/event.h>
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/* IED scripts are no longer used by UEFI/RM from Ampere, but have been updated for
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* the x86 option ROM. However, the relevant VBIOS table versions weren't modified,
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* so we're unable to detect this in a nice way.
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*/
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#define AMPERE_IED_HACK(disp) ((disp)->engine.subdev.device->card_type >= GA100)
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static int
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nvkm_dp_mst_id_put(struct nvkm_outp *outp, u32 id)
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{
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return 0;
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}
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static int
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nvkm_dp_mst_id_get(struct nvkm_outp *outp, u32 *pid)
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{
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*pid = BIT(outp->index);
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return 0;
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}
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static int
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nvkm_dp_aux_xfer(struct nvkm_outp *outp, u8 type, u32 addr, u8 *data, u8 *size)
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{
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int ret = nvkm_i2c_aux_acquire(outp->dp.aux);
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if (ret)
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return ret;
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ret = nvkm_i2c_aux_xfer(outp->dp.aux, false, type, addr, data, size);
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nvkm_i2c_aux_release(outp->dp.aux);
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return ret;
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}
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static int
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nvkm_dp_aux_pwr(struct nvkm_outp *outp, bool pu)
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{
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outp->dp.enabled = pu;
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nvkm_dp_enable(outp, outp->dp.enabled);
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return 0;
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}
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struct lt_state {
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struct nvkm_outp *outp;
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int repeaters;
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int repeater;
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u8 stat[6];
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u8 conf[4];
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bool pc2;
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u8 pc2stat;
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u8 pc2conf[2];
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};
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static int
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nvkm_dp_train_sense(struct lt_state *lt, bool pc, u32 delay)
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{
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struct nvkm_outp *outp = lt->outp;
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u32 addr;
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int ret;
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usleep_range(delay, delay * 2);
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if (lt->repeater)
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addr = DPCD_LTTPR_LANE0_1_STATUS(lt->repeater);
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else
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addr = DPCD_LS02;
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ret = nvkm_rdaux(outp->dp.aux, addr, <->stat[0], 3);
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if (ret)
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return ret;
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if (lt->repeater)
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addr = DPCD_LTTPR_LANE0_1_ADJUST(lt->repeater);
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else
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addr = DPCD_LS06;
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ret = nvkm_rdaux(outp->dp.aux, addr, <->stat[4], 2);
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if (ret)
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return ret;
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if (pc) {
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ret = nvkm_rdaux(outp->dp.aux, DPCD_LS0C, <->pc2stat, 1);
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if (ret)
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lt->pc2stat = 0x00;
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OUTP_TRACE(outp, "status %6ph pc2 %02x", lt->stat, lt->pc2stat);
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} else {
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OUTP_TRACE(outp, "status %6ph", lt->stat);
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}
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return 0;
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}
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static int
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nvkm_dp_train_drive(struct lt_state *lt, bool pc)
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{
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struct nvkm_outp *outp = lt->outp;
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struct nvkm_ior *ior = outp->ior;
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struct nvkm_bios *bios = ior->disp->engine.subdev.device->bios;
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struct nvbios_dpout info;
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struct nvbios_dpcfg ocfg;
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u8 ver, hdr, cnt, len;
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u32 addr;
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u32 data;
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int ret, i;
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for (i = 0; i < ior->dp.nr; i++) {
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u8 lane = (lt->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
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u8 lpc2 = (lt->pc2stat >> (i * 2)) & 0x3;
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u8 lpre = (lane & 0x0c) >> 2;
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u8 lvsw = (lane & 0x03) >> 0;
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u8 hivs = 3 - lpre;
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u8 hipe = 3;
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u8 hipc = 3;
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if (lpc2 >= hipc)
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lpc2 = hipc | DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED;
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if (lpre >= hipe) {
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lpre = hipe | DPCD_LC03_MAX_SWING_REACHED; /* yes. */
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lvsw = hivs = 3 - (lpre & 3);
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} else
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if (lvsw >= hivs) {
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lvsw = hivs | DPCD_LC03_MAX_SWING_REACHED;
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}
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lt->conf[i] = (lpre << 3) | lvsw;
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lt->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4);
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OUTP_TRACE(outp, "config lane %d %02x %02x", i, lt->conf[i], lpc2);
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if (lt->repeater != lt->repeaters)
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continue;
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data = nvbios_dpout_match(bios, outp->info.hasht, outp->info.hashm,
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&ver, &hdr, &cnt, &len, &info);
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if (!data)
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continue;
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data = nvbios_dpcfg_match(bios, data, lpc2 & 3, lvsw & 3, lpre & 3,
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&ver, &hdr, &cnt, &len, &ocfg);
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if (!data)
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continue;
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ior->func->dp->drive(ior, i, ocfg.pc, ocfg.dc, ocfg.pe, ocfg.tx_pu);
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}
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if (lt->repeater)
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addr = DPCD_LTTPR_LANE0_SET(lt->repeater);
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else
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addr = DPCD_LC03(0);
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ret = nvkm_wraux(outp->dp.aux, addr, lt->conf, 4);
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if (ret)
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return ret;
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if (pc) {
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ret = nvkm_wraux(outp->dp.aux, DPCD_LC0F, lt->pc2conf, 2);
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if (ret)
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return ret;
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}
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return 0;
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}
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static void
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nvkm_dp_train_pattern(struct lt_state *lt, u8 pattern)
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{
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struct nvkm_outp *outp = lt->outp;
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u32 addr;
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u8 sink_tp;
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OUTP_TRACE(outp, "training pattern %d", pattern);
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outp->ior->func->dp->pattern(outp->ior, pattern);
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if (lt->repeater)
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addr = DPCD_LTTPR_PATTERN_SET(lt->repeater);
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else
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addr = DPCD_LC02;
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nvkm_rdaux(outp->dp.aux, addr, &sink_tp, 1);
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sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET;
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sink_tp |= (pattern != 4) ? pattern : 7;
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if (pattern != 0)
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sink_tp |= DPCD_LC02_SCRAMBLING_DISABLE;
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else
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sink_tp &= ~DPCD_LC02_SCRAMBLING_DISABLE;
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nvkm_wraux(outp->dp.aux, addr, &sink_tp, 1);
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}
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static int
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nvkm_dp_train_eq(struct lt_state *lt)
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{
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struct nvkm_i2c_aux *aux = lt->outp->dp.aux;
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bool eq_done = false, cr_done = true;
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int tries = 0, usec = 0, i;
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u8 data;
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if (lt->repeater) {
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if (!nvkm_rdaux(aux, DPCD_LTTPR_AUX_RD_INTERVAL(lt->repeater), &data, sizeof(data)))
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usec = (data & DPCD_RC0E_AUX_RD_INTERVAL) * 4000;
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nvkm_dp_train_pattern(lt, 4);
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} else {
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if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x14 &&
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lt->outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED)
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nvkm_dp_train_pattern(lt, 4);
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else
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if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x12 &&
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lt->outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED)
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nvkm_dp_train_pattern(lt, 3);
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else
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nvkm_dp_train_pattern(lt, 2);
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usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000;
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}
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do {
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if ((tries &&
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nvkm_dp_train_drive(lt, lt->pc2)) ||
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nvkm_dp_train_sense(lt, lt->pc2, usec ? usec : 400))
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break;
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eq_done = !!(lt->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE);
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for (i = 0; i < lt->outp->ior->dp.nr && eq_done; i++) {
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u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
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if (!(lane & DPCD_LS02_LANE0_CR_DONE))
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cr_done = false;
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if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
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!(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
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eq_done = false;
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}
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} while (!eq_done && cr_done && ++tries <= 5);
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return eq_done ? 0 : -1;
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}
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static int
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nvkm_dp_train_cr(struct lt_state *lt)
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{
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bool cr_done = false, abort = false;
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int voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
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int tries = 0, usec = 0, i;
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nvkm_dp_train_pattern(lt, 1);
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if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] < 0x14 && !lt->repeater)
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usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000;
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do {
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if (nvkm_dp_train_drive(lt, false) ||
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nvkm_dp_train_sense(lt, false, usec ? usec : 100))
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break;
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cr_done = true;
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for (i = 0; i < lt->outp->ior->dp.nr; i++) {
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u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
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if (!(lane & DPCD_LS02_LANE0_CR_DONE)) {
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cr_done = false;
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if (lt->conf[i] & DPCD_LC03_MAX_SWING_REACHED)
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abort = true;
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break;
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}
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}
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if ((lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) {
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voltage = lt->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
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tries = 0;
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}
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} while (!cr_done && !abort && ++tries < 5);
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return cr_done ? 0 : -1;
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}
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static int
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nvkm_dp_train_link(struct nvkm_outp *outp, int rate)
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{
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struct nvkm_ior *ior = outp->ior;
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struct lt_state lt = {
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.outp = outp,
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.pc2 = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED,
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.repeaters = outp->dp.lttprs,
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};
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u8 sink[2];
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int ret;
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OUTP_DBG(outp, "training %dx%02x", ior->dp.nr, ior->dp.bw);
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/* Set desired link configuration on the sink. */
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sink[0] = (outp->dp.rate[rate].dpcd < 0) ? ior->dp.bw : 0;
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sink[1] = ior->dp.nr;
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if (ior->dp.ef)
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sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN;
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if (outp->dp.lt.post_adj)
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sink[1] |= 0x20;
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ret = nvkm_wraux(outp->dp.aux, DPCD_LC00_LINK_BW_SET, sink, 2);
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if (ret)
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return ret;
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if (outp->dp.rate[rate].dpcd >= 0) {
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ret = nvkm_rdaux(outp->dp.aux, DPCD_LC15_LINK_RATE_SET, &sink[0], sizeof(sink[0]));
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if (ret)
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return ret;
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sink[0] &= ~DPCD_LC15_LINK_RATE_SET_MASK;
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sink[0] |= outp->dp.rate[rate].dpcd;
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ret = nvkm_wraux(outp->dp.aux, DPCD_LC15_LINK_RATE_SET, &sink[0], sizeof(sink[0]));
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if (ret)
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return ret;
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}
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/* Attempt to train the link in this configuration. */
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for (lt.repeater = lt.repeaters; lt.repeater >= 0; lt.repeater--) {
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if (lt.repeater)
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OUTP_DBG(outp, "training LTTPR%d", lt.repeater);
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else
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OUTP_DBG(outp, "training sink");
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memset(lt.stat, 0x00, sizeof(lt.stat));
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ret = nvkm_dp_train_cr(<);
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if (ret == 0)
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ret = nvkm_dp_train_eq(<);
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nvkm_dp_train_pattern(<, 0);
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}
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return ret;
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}
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static int
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nvkm_dp_train_links(struct nvkm_outp *outp, int rate)
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{
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struct nvkm_ior *ior = outp->ior;
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struct nvkm_disp *disp = outp->disp;
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struct nvkm_subdev *subdev = &disp->engine.subdev;
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struct nvkm_bios *bios = subdev->device->bios;
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u32 lnkcmp;
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int ret;
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OUTP_DBG(outp, "programming link for %dx%02x", ior->dp.nr, ior->dp.bw);
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/* Intersect misc. capabilities of the OR and sink. */
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if (disp->engine.subdev.device->chipset < 0x110)
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outp->dp.dpcd[DPCD_RC03] &= ~DPCD_RC03_TPS4_SUPPORTED;
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if (disp->engine.subdev.device->chipset < 0xd0)
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outp->dp.dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED;
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if (AMPERE_IED_HACK(disp) && (lnkcmp = outp->dp.info.script[0])) {
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/* Execute BeforeLinkTraining script from DP Info table. */
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while (ior->dp.bw < nvbios_rd08(bios, lnkcmp))
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lnkcmp += 3;
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lnkcmp = nvbios_rd16(bios, lnkcmp + 1);
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nvbios_init(&outp->disp->engine.subdev, lnkcmp,
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init.outp = &outp->info;
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init.or = ior->id;
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init.link = ior->asy.link;
|
||
|
);
|
||
|
}
|
||
|
|
||
|
/* Set desired link configuration on the source. */
|
||
|
if ((lnkcmp = outp->dp.info.lnkcmp)) {
|
||
|
if (outp->dp.version < 0x30) {
|
||
|
while ((ior->dp.bw * 2700) < nvbios_rd16(bios, lnkcmp))
|
||
|
lnkcmp += 4;
|
||
|
lnkcmp = nvbios_rd16(bios, lnkcmp + 2);
|
||
|
} else {
|
||
|
while (ior->dp.bw < nvbios_rd08(bios, lnkcmp))
|
||
|
lnkcmp += 3;
|
||
|
lnkcmp = nvbios_rd16(bios, lnkcmp + 1);
|
||
|
}
|
||
|
|
||
|
nvbios_init(subdev, lnkcmp,
|
||
|
init.outp = &outp->info;
|
||
|
init.or = ior->id;
|
||
|
init.link = ior->asy.link;
|
||
|
);
|
||
|
}
|
||
|
|
||
|
ret = ior->func->dp->links(ior, outp->dp.aux);
|
||
|
if (ret) {
|
||
|
if (ret < 0) {
|
||
|
OUTP_ERR(outp, "train failed with %d", ret);
|
||
|
return ret;
|
||
|
}
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
ior->func->dp->power(ior, ior->dp.nr);
|
||
|
|
||
|
/* Attempt to train the link in this configuration. */
|
||
|
return nvkm_dp_train_link(outp, rate);
|
||
|
}
|
||
|
|
||
|
static void
|
||
|
nvkm_dp_train_fini(struct nvkm_outp *outp)
|
||
|
{
|
||
|
/* Execute AfterLinkTraining script from DP Info table. */
|
||
|
nvbios_init(&outp->disp->engine.subdev, outp->dp.info.script[1],
|
||
|
init.outp = &outp->info;
|
||
|
init.or = outp->ior->id;
|
||
|
init.link = outp->ior->asy.link;
|
||
|
);
|
||
|
}
|
||
|
|
||
|
static void
|
||
|
nvkm_dp_train_init(struct nvkm_outp *outp)
|
||
|
{
|
||
|
/* Execute EnableSpread/DisableSpread script from DP Info table. */
|
||
|
if (outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_MAX_DOWNSPREAD) {
|
||
|
nvbios_init(&outp->disp->engine.subdev, outp->dp.info.script[2],
|
||
|
init.outp = &outp->info;
|
||
|
init.or = outp->ior->id;
|
||
|
init.link = outp->ior->asy.link;
|
||
|
);
|
||
|
} else {
|
||
|
nvbios_init(&outp->disp->engine.subdev, outp->dp.info.script[3],
|
||
|
init.outp = &outp->info;
|
||
|
init.or = outp->ior->id;
|
||
|
init.link = outp->ior->asy.link;
|
||
|
);
|
||
|
}
|
||
|
|
||
|
if (!AMPERE_IED_HACK(outp->disp)) {
|
||
|
/* Execute BeforeLinkTraining script from DP Info table. */
|
||
|
nvbios_init(&outp->disp->engine.subdev, outp->dp.info.script[0],
|
||
|
init.outp = &outp->info;
|
||
|
init.or = outp->ior->id;
|
||
|
init.link = outp->ior->asy.link;
|
||
|
);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
static int
|
||
|
nvkm_dp_drive(struct nvkm_outp *outp, u8 lanes, u8 pe[4], u8 vs[4])
|
||
|
{
|
||
|
struct lt_state lt = {
|
||
|
.outp = outp,
|
||
|
.stat[4] = (pe[0] << 2) | (vs[0] << 0) |
|
||
|
(pe[1] << 6) | (vs[1] << 4),
|
||
|
.stat[5] = (pe[2] << 2) | (vs[2] << 0) |
|
||
|
(pe[3] << 6) | (vs[3] << 4),
|
||
|
};
|
||
|
|
||
|
return nvkm_dp_train_drive(<, false);
|
||
|
}
|
||
|
|
||
|
static int
|
||
|
nvkm_dp_train(struct nvkm_outp *outp, bool retrain)
|
||
|
{
|
||
|
struct nvkm_ior *ior = outp->ior;
|
||
|
int ret, rate;
|
||
|
|
||
|
for (rate = 0; rate < outp->dp.rates; rate++) {
|
||
|
if (outp->dp.rate[rate].rate == (retrain ? ior->dp.bw : outp->dp.lt.bw) * 27000)
|
||
|
break;
|
||
|
}
|
||
|
|
||
|
if (WARN_ON(rate == outp->dp.rates))
|
||
|
return -EINVAL;
|
||
|
|
||
|
/* Retraining link? Skip source configuration, it can mess up the active modeset. */
|
||
|
if (retrain) {
|
||
|
mutex_lock(&outp->dp.mutex);
|
||
|
ret = nvkm_dp_train_link(outp, rate);
|
||
|
mutex_unlock(&outp->dp.mutex);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
mutex_lock(&outp->dp.mutex);
|
||
|
OUTP_DBG(outp, "training");
|
||
|
|
||
|
ior->dp.mst = outp->dp.lt.mst;
|
||
|
ior->dp.ef = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP;
|
||
|
ior->dp.bw = outp->dp.lt.bw;
|
||
|
ior->dp.nr = outp->dp.lt.nr;
|
||
|
|
||
|
nvkm_dp_train_init(outp);
|
||
|
ret = nvkm_dp_train_links(outp, rate);
|
||
|
nvkm_dp_train_fini(outp);
|
||
|
if (ret < 0)
|
||
|
OUTP_ERR(outp, "training failed");
|
||
|
else
|
||
|
OUTP_DBG(outp, "training done");
|
||
|
|
||
|
mutex_unlock(&outp->dp.mutex);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
void
|
||
|
nvkm_dp_disable(struct nvkm_outp *outp, struct nvkm_ior *ior)
|
||
|
{
|
||
|
/* Execute DisableLT script from DP Info Table. */
|
||
|
nvbios_init(&ior->disp->engine.subdev, outp->dp.info.script[4],
|
||
|
init.outp = &outp->info;
|
||
|
init.or = ior->id;
|
||
|
init.link = ior->arm.link;
|
||
|
);
|
||
|
}
|
||
|
|
||
|
static void
|
||
|
nvkm_dp_release(struct nvkm_outp *outp)
|
||
|
{
|
||
|
outp->ior->dp.nr = 0;
|
||
|
nvkm_dp_disable(outp, outp->ior);
|
||
|
|
||
|
nvkm_outp_release(outp);
|
||
|
}
|
||
|
|
||
|
void
|
||
|
nvkm_dp_enable(struct nvkm_outp *outp, bool auxpwr)
|
||
|
{
|
||
|
struct nvkm_gpio *gpio = outp->disp->engine.subdev.device->gpio;
|
||
|
struct nvkm_i2c_aux *aux = outp->dp.aux;
|
||
|
|
||
|
if (auxpwr && !outp->dp.aux_pwr) {
|
||
|
/* eDP panels need powering on by us (if the VBIOS doesn't default it
|
||
|
* to on) before doing any AUX channel transactions. LVDS panel power
|
||
|
* is handled by the SOR itself, and not required for LVDS DDC.
|
||
|
*/
|
||
|
if (outp->conn->info.type == DCB_CONNECTOR_eDP) {
|
||
|
int power = nvkm_gpio_get(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff);
|
||
|
if (power == 0) {
|
||
|
nvkm_gpio_set(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff, 1);
|
||
|
outp->dp.aux_pwr_pu = true;
|
||
|
}
|
||
|
|
||
|
/* We delay here unconditionally, even if already powered,
|
||
|
* because some laptop panels having a significant resume
|
||
|
* delay before the panel begins responding.
|
||
|
*
|
||
|
* This is likely a bit of a hack, but no better idea for
|
||
|
* handling this at the moment.
|
||
|
*/
|
||
|
msleep(300);
|
||
|
}
|
||
|
|
||
|
OUTP_DBG(outp, "aux power -> always");
|
||
|
nvkm_i2c_aux_monitor(aux, true);
|
||
|
outp->dp.aux_pwr = true;
|
||
|
} else
|
||
|
if (!auxpwr && outp->dp.aux_pwr) {
|
||
|
OUTP_DBG(outp, "aux power -> demand");
|
||
|
nvkm_i2c_aux_monitor(aux, false);
|
||
|
outp->dp.aux_pwr = false;
|
||
|
|
||
|
/* Restore eDP panel GPIO to its prior state if we changed it, as
|
||
|
* it could potentially interfere with other outputs.
|
||
|
*/
|
||
|
if (outp->conn->info.type == DCB_CONNECTOR_eDP) {
|
||
|
if (outp->dp.aux_pwr_pu) {
|
||
|
nvkm_gpio_set(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff, 0);
|
||
|
outp->dp.aux_pwr_pu = false;
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
}
|
||
|
|
||
|
static void
|
||
|
nvkm_dp_fini(struct nvkm_outp *outp)
|
||
|
{
|
||
|
nvkm_dp_enable(outp, false);
|
||
|
}
|
||
|
|
||
|
static void
|
||
|
nvkm_dp_init(struct nvkm_outp *outp)
|
||
|
{
|
||
|
nvkm_outp_init(outp);
|
||
|
nvkm_dp_enable(outp, outp->dp.enabled);
|
||
|
}
|
||
|
|
||
|
static void *
|
||
|
nvkm_dp_dtor(struct nvkm_outp *outp)
|
||
|
{
|
||
|
return outp;
|
||
|
}
|
||
|
|
||
|
static const struct nvkm_outp_func
|
||
|
nvkm_dp_func = {
|
||
|
.dtor = nvkm_dp_dtor,
|
||
|
.init = nvkm_dp_init,
|
||
|
.fini = nvkm_dp_fini,
|
||
|
.detect = nvkm_outp_detect,
|
||
|
.inherit = nvkm_outp_inherit,
|
||
|
.acquire = nvkm_outp_acquire,
|
||
|
.release = nvkm_dp_release,
|
||
|
.bl.get = nvkm_outp_bl_get,
|
||
|
.bl.set = nvkm_outp_bl_set,
|
||
|
.dp.aux_pwr = nvkm_dp_aux_pwr,
|
||
|
.dp.aux_xfer = nvkm_dp_aux_xfer,
|
||
|
.dp.train = nvkm_dp_train,
|
||
|
.dp.drive = nvkm_dp_drive,
|
||
|
.dp.mst_id_get = nvkm_dp_mst_id_get,
|
||
|
.dp.mst_id_put = nvkm_dp_mst_id_put,
|
||
|
};
|
||
|
|
||
|
int
|
||
|
nvkm_dp_new(struct nvkm_disp *disp, int index, struct dcb_output *dcbE, struct nvkm_outp **poutp)
|
||
|
{
|
||
|
struct nvkm_device *device = disp->engine.subdev.device;
|
||
|
struct nvkm_bios *bios = device->bios;
|
||
|
struct nvkm_i2c *i2c = device->i2c;
|
||
|
struct nvkm_outp *outp;
|
||
|
u8 ver, hdr, cnt, len;
|
||
|
u32 data;
|
||
|
int ret;
|
||
|
|
||
|
ret = nvkm_outp_new_(&nvkm_dp_func, disp, index, dcbE, poutp);
|
||
|
outp = *poutp;
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
|
||
|
if (dcbE->location == 0)
|
||
|
outp->dp.aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_CCB(dcbE->i2c_index));
|
||
|
else
|
||
|
outp->dp.aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbE->extdev));
|
||
|
if (!outp->dp.aux) {
|
||
|
OUTP_ERR(outp, "no aux");
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
|
||
|
/* bios data is not optional */
|
||
|
data = nvbios_dpout_match(bios, outp->info.hasht, outp->info.hashm,
|
||
|
&outp->dp.version, &hdr, &cnt, &len, &outp->dp.info);
|
||
|
if (!data) {
|
||
|
OUTP_ERR(outp, "no bios dp data");
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
|
||
|
OUTP_DBG(outp, "bios dp %02x %02x %02x %02x", outp->dp.version, hdr, cnt, len);
|
||
|
|
||
|
data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
|
||
|
outp->dp.mst = data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
|
||
|
|
||
|
mutex_init(&outp->dp.mutex);
|
||
|
return 0;
|
||
|
}
|