50 lines
1.2 KiB
C
50 lines
1.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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/* Copyright (c) 2023 Imagination Technologies Ltd. */
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#ifndef PVR_FW_MIPS_H
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#define PVR_FW_MIPS_H
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#include "pvr_rogue_mips.h"
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#include <asm/page.h>
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#include <linux/math.h>
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#include <linux/types.h>
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/* Forward declaration from pvr_gem.h. */
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struct pvr_gem_object;
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#define PVR_MIPS_PT_PAGE_COUNT DIV_ROUND_UP(ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES * ROGUE_MIPSFW_PAGE_SIZE_4K, PAGE_SIZE)
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/**
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* struct pvr_fw_mips_data - MIPS-specific data
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*/
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struct pvr_fw_mips_data {
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/**
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* @pt_pages: Pages containing MIPS pagetable.
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*/
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struct page *pt_pages[PVR_MIPS_PT_PAGE_COUNT];
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/** @pt: Pointer to CPU mapping of MIPS pagetable. */
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u32 *pt;
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/** @pt_dma_addr: DMA mappings of MIPS pagetable. */
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dma_addr_t pt_dma_addr[PVR_MIPS_PT_PAGE_COUNT];
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/** @boot_code_dma_addr: DMA address of MIPS boot code. */
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dma_addr_t boot_code_dma_addr;
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/** @boot_data_dma_addr: DMA address of MIPS boot data. */
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dma_addr_t boot_data_dma_addr;
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/** @exception_code_dma_addr: DMA address of MIPS exception code. */
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dma_addr_t exception_code_dma_addr;
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/** @cache_policy: Cache policy for this processor. */
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u32 cache_policy;
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/** @pfn_mask: PFN mask for MIPS pagetable. */
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u32 pfn_mask;
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};
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#endif /* PVR_FW_MIPS_H */
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