276 lines
8.4 KiB
Plaintext
276 lines
8.4 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/G2UL SoC
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
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#include "r9a07g043.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a55";
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reg = <0>;
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device_type = "cpu";
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#cooling-cells = <2>;
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next-level-cache = <&L3_CA55>;
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
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operating-points-v2 = <&cluster0_opp>;
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};
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L3_CA55: cache-controller-0 {
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compatible = "cache";
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cache-unified;
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cache-size = <0x40000>;
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cache-level = <3>;
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};
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};
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pmu {
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compatible = "arm,cortex-a55-pmu";
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interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
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<&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
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"hyp-virt";
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};
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};
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&soc {
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interrupt-parent = <&gic>;
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cru: video@10830000 {
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compatible = "renesas,r9a07g043-cru", "renesas,rzg2l-cru";
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reg = <0 0x10830000 0 0x400>;
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clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>,
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<&cpg CPG_MOD R9A07G043_CRU_PCLK>,
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<&cpg CPG_MOD R9A07G043_CRU_ACLK>;
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clock-names = "video", "apb", "axi";
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interrupts = <SOC_PERIPHERAL_IRQ(167) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(168) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(169) IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
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resets = <&cpg R9A07G043_CRU_PRESETN>,
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<&cpg R9A07G043_CRU_ARESETN>;
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reset-names = "presetn", "aresetn";
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power-domains = <&cpg>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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crucsi2: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&csi2cru>;
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};
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};
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};
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};
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csi2: csi2@10830400 {
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compatible = "renesas,r9a07g043-csi2", "renesas,rzg2l-csi2";
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reg = <0 0x10830400 0 0xfc00>;
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interrupts = <SOC_PERIPHERAL_IRQ(166) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A07G043_CRU_SYSCLK>,
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<&cpg CPG_MOD R9A07G043_CRU_VCLK>,
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<&cpg CPG_MOD R9A07G043_CRU_PCLK>;
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clock-names = "system", "video", "apb";
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resets = <&cpg R9A07G043_CRU_PRESETN>,
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<&cpg R9A07G043_CRU_CMN_RSTB>;
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reset-names = "presetn", "cmn-rstb";
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power-domains = <&cpg>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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csi2cru: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&crucsi2>;
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};
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};
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};
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};
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vspd: vsp@10870000 {
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compatible = "renesas,r9a07g043u-vsp2", "renesas,r9a07g044-vsp2";
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reg = <0 0x10870000 0 0x10000>;
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interrupts = <SOC_PERIPHERAL_IRQ(149) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>,
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<&cpg CPG_MOD R9A07G043_LCDC_CLK_P>,
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<&cpg CPG_MOD R9A07G043_LCDC_CLK_D>;
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clock-names = "aclk", "pclk", "vclk";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_LCDC_RESET_N>;
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renesas,fcp = <&fcpvd>;
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};
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fcpvd: fcp@10880000 {
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compatible = "renesas,r9a07g043u-fcpvd", "renesas,fcpv";
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reg = <0 0x10880000 0 0x10000>;
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clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>,
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<&cpg CPG_MOD R9A07G043_LCDC_CLK_P>,
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<&cpg CPG_MOD R9A07G043_LCDC_CLK_D>;
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clock-names = "aclk", "pclk", "vclk";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_LCDC_RESET_N>;
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};
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du: display@10890000 {
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compatible = "renesas,r9a07g043u-du";
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reg = <0 0x10890000 0 0x10000>;
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interrupts = <SOC_PERIPHERAL_IRQ(152) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>,
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<&cpg CPG_MOD R9A07G043_LCDC_CLK_P>,
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<&cpg CPG_MOD R9A07G043_LCDC_CLK_D>;
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clock-names = "aclk", "pclk", "vclk";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_LCDC_RESET_N>;
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renesas,vsps = <&vspd 0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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du_out_rgb: endpoint {
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};
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};
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};
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};
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irqc: interrupt-controller@110a0000 {
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compatible = "renesas,r9a07g043u-irqc",
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"renesas,rzg2l-irqc";
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reg = <0 0x110a0000 0 0x10000>;
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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interrupts = <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(8) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(444) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(445) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(446) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(447) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(448) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(449) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(450) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(451) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(452) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(453) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(454) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(455) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(456) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(457) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(458) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(459) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(460) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(461) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(462) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(463) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(464) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(465) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(466) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(467) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(468) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(469) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(470) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(471) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(472) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>,
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<SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_EDGE_RISING>,
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<SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_EDGE_RISING>,
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<SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_EDGE_RISING>,
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<SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_EDGE_RISING>,
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<SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_EDGE_RISING>,
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<SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "nmi",
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"irq0", "irq1", "irq2", "irq3",
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"irq4", "irq5", "irq6", "irq7",
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"tint0", "tint1", "tint2", "tint3",
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"tint4", "tint5", "tint6", "tint7",
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"tint8", "tint9", "tint10", "tint11",
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"tint12", "tint13", "tint14", "tint15",
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"tint16", "tint17", "tint18", "tint19",
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"tint20", "tint21", "tint22", "tint23",
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"tint24", "tint25", "tint26", "tint27",
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"tint28", "tint29", "tint30", "tint31",
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"bus-err", "ec7tie1-0", "ec7tie2-0",
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"ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
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"ec7tiovf-1";
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clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>,
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<&cpg CPG_MOD R9A07G043_IA55_PCLK>;
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clock-names = "clk", "pclk";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_IA55_RESETN>;
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};
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gic: interrupt-controller@11900000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0x11900000 0 0x20000>,
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<0x0 0x11940000 0 0x40000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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&sysc {
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interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
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<SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "lpm_int", "ca55stbydone_int",
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"cm33stbyr_int", "ca55_deny";
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};
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