45 lines
1.9 KiB
ReStructuredText
45 lines
1.9 KiB
ReStructuredText
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.. SPDX-License-Identifier: GPL-2.0
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===================================
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Memory copy/set instructions (MOPS)
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===================================
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A MOPS memory copy/set operation consists of three consecutive CPY* or SET*
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instructions: a prologue, main and epilogue (for example: CPYP, CPYM, CPYE).
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A main or epilogue instruction can take a MOPS exception for various reasons,
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for example when a task is migrated to a CPU with a different MOPS
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implementation, or when the instruction's alignment and size requirements are
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not met. The software exception handler is then expected to reset the registers
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and restart execution from the prologue instruction. Normally this is handled
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by the kernel.
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For more details refer to "D1.3.5.7 Memory Copy and Memory Set exceptions" in
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the Arm Architecture Reference Manual DDI 0487K.a (Arm ARM).
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.. _arm64_mops_hyp:
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Hypervisor requirements
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-----------------------
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A hypervisor running a Linux guest must handle all MOPS exceptions from the
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guest kernel, as Linux may not be able to handle the exception at all times.
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For example, a MOPS exception can be taken when the hypervisor migrates a vCPU
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to another physical CPU with a different MOPS implementation.
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To do this, the hypervisor must:
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- Set HCRX_EL2.MCE2 to 1 so that the exception is taken to the hypervisor.
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- Have an exception handler that implements the algorithm from the Arm ARM
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rules CNTMJ and MWFQH.
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- Set the guest's PSTATE.SS to 0 in the exception handler, to handle a
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potential step of the current instruction.
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Note: Clearing PSTATE.SS is needed so that a single step exception is taken
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on the next instruction (the prologue instruction). Otherwise prologue
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would get silently stepped over and the single step exception taken on the
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main instruction. Note that if the guest instruction is not being stepped
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then clearing PSTATE.SS has no effect.
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