40 lines
1.0 KiB
C
40 lines
1.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copied from the kernel sources to tools/arch/riscv:
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*
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2013 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#ifndef _TOOLS_LINUX_ASM_RISCV_BARRIER_H
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#define _TOOLS_LINUX_ASM_RISCV_BARRIER_H
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#include <asm/fence.h>
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#include <linux/compiler.h>
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/* These barriers need to enforce ordering on both devices and memory. */
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#define mb() RISCV_FENCE(iorw, iorw)
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#define rmb() RISCV_FENCE(ir, ir)
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#define wmb() RISCV_FENCE(ow, ow)
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/* These barriers do not need to enforce ordering on devices, just memory. */
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#define smp_mb() RISCV_FENCE(rw, rw)
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#define smp_rmb() RISCV_FENCE(r, r)
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#define smp_wmb() RISCV_FENCE(w, w)
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#define smp_store_release(p, v) \
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do { \
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RISCV_FENCE(rw, w); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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RISCV_FENCE(r, rw); \
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___p1; \
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})
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#endif /* _TOOLS_LINUX_ASM_RISCV_BARRIER_H */
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