264 lines
7.3 KiB
C
264 lines
7.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* AMD ALSA SoC PDM Driver
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*
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* Copyright (C) 2022, 2023 Advanced Micro Devices, Inc. All rights reserved.
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*/
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#include <linux/soundwire/sdw_amd.h>
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#include <sound/acp63_chip_offset_byte.h>
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#define ACP_DEVICE_ID 0x15E2
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#define ACP63_REG_START 0x1240000
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#define ACP63_REG_END 0x125C000
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#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
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#define ACP_PGFSM_CNTL_POWER_ON_MASK 1
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#define ACP_PGFSM_CNTL_POWER_OFF_MASK 0
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#define ACP_PGFSM_STATUS_MASK 3
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#define ACP_POWERED_ON 0
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#define ACP_POWER_ON_IN_PROGRESS 1
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#define ACP_POWERED_OFF 2
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#define ACP_POWER_OFF_IN_PROGRESS 3
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#define ACP_ERROR_MASK 0x20000000
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#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
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#define PDM_DMA_STAT 0x10
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#define PDM_DMA_INTR_MASK 0x10000
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#define ACP_ERROR_STAT 29
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#define PDM_DECIMATION_FACTOR 2
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#define ACP_PDM_CLK_FREQ_MASK 7
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#define ACP_WOV_GAIN_CONTROL GENMASK(4, 3)
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#define ACP_PDM_ENABLE 1
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#define ACP_PDM_DISABLE 0
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#define ACP_PDM_DMA_EN_STATUS 2
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#define TWO_CH 2
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#define DELAY_US 5
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#define ACP_COUNTER 20000
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#define ACP_SRAM_PTE_OFFSET 0x03800000
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#define PAGE_SIZE_4K_ENABLE 2
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#define PDM_PTE_OFFSET 0
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#define PDM_MEM_WINDOW_START 0x4000000
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#define CAPTURE_MIN_NUM_PERIODS 4
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#define CAPTURE_MAX_NUM_PERIODS 4
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#define CAPTURE_MAX_PERIOD_SIZE 8192
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#define CAPTURE_MIN_PERIOD_SIZE 4096
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#define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)
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#define MIN_BUFFER MAX_BUFFER
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/* time in ms for runtime suspend delay */
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#define ACP_SUSPEND_DELAY_MS 2000
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#define ACP_DMIC_DEV 2
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#define ACP63_DMIC_ADDR 2
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#define ACP63_SDW_ADDR 5
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#define AMD_SDW_MAX_MANAGERS 2
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/* time in ms for acp timeout */
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#define ACP_TIMEOUT 500
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#define ACP_SDW0_STAT BIT(21)
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#define ACP_SDW1_STAT BIT(2)
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#define ACP_ERROR_IRQ BIT(29)
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#define ACP_AUDIO0_TX_THRESHOLD 0x1c
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#define ACP_AUDIO1_TX_THRESHOLD 0x1a
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#define ACP_AUDIO2_TX_THRESHOLD 0x18
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#define ACP_AUDIO0_RX_THRESHOLD 0x1b
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#define ACP_AUDIO1_RX_THRESHOLD 0x19
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#define ACP_AUDIO2_RX_THRESHOLD 0x17
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#define ACP_P1_AUDIO1_TX_THRESHOLD BIT(6)
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#define ACP_P1_AUDIO1_RX_THRESHOLD BIT(5)
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#define ACP_SDW_DMA_IRQ_MASK 0x1F800000
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#define ACP_P1_SDW_DMA_IRQ_MASK 0x60
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#define ACP63_SDW0_DMA_MAX_STREAMS 6
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#define ACP63_SDW1_DMA_MAX_STREAMS 2
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#define ACP_P1_AUDIO_TX_THRESHOLD 6
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/*
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* Below entries describes SDW0 instance DMA stream id and DMA irq bit mapping
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* in ACP_EXTENAL_INTR_CNTL register.
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* Stream id IRQ Bit
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* 0 (SDW0_AUDIO0_TX) 28
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* 1 (SDW0_AUDIO1_TX) 26
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* 2 (SDW0_AUDIO2_TX) 24
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* 3 (SDW0_AUDIO0_RX) 27
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* 4 (SDW0_AUDIO1_RX) 25
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* 5 (SDW0_AUDIO2_RX) 23
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*/
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#define SDW0_DMA_TX_IRQ_MASK(i) (ACP_AUDIO0_TX_THRESHOLD - (2 * (i)))
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#define SDW0_DMA_RX_IRQ_MASK(i) (ACP_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3)))
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/*
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* Below entries describes SDW1 instance DMA stream id and DMA irq bit mapping
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* in ACP_EXTENAL_INTR_CNTL1 register.
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* Stream id IRQ Bit
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* 0 (SDW1_AUDIO1_TX) 6
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* 1 (SDW1_AUDIO1_RX) 5
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*/
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#define SDW1_DMA_IRQ_MASK(i) (ACP_P1_AUDIO_TX_THRESHOLD - (i))
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#define ACP_DELAY_US 5
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#define ACP_SDW_RING_BUFF_ADDR_OFFSET (128 * 1024)
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#define SDW0_MEM_WINDOW_START 0x4800000
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#define ACP_SDW_SRAM_PTE_OFFSET 0x03800400
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#define SDW0_PTE_OFFSET 0x400
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#define SDW_FIFO_SIZE 0x100
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#define SDW_DMA_SIZE 0x40
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#define ACP_SDW0_FIFO_OFFSET 0x100
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#define ACP_SDW_PTE_OFFSET 0x100
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#define SDW_FIFO_OFFSET 0x100
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#define SDW_PTE_OFFSET(i) (SDW0_PTE_OFFSET + ((i) * 0x600))
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#define ACP_SDW_FIFO_OFFSET(i) (ACP_SDW0_FIFO_OFFSET + ((i) * 0x500))
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#define SDW_MEM_WINDOW_START(i) (SDW0_MEM_WINDOW_START + ((i) * 0xC0000))
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#define SDW_PLAYBACK_MIN_NUM_PERIODS 2
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#define SDW_PLAYBACK_MAX_NUM_PERIODS 8
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#define SDW_PLAYBACK_MAX_PERIOD_SIZE 8192
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#define SDW_PLAYBACK_MIN_PERIOD_SIZE 1024
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#define SDW_CAPTURE_MIN_NUM_PERIODS 2
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#define SDW_CAPTURE_MAX_NUM_PERIODS 8
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#define SDW_CAPTURE_MAX_PERIOD_SIZE 8192
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#define SDW_CAPTURE_MIN_PERIOD_SIZE 1024
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#define SDW_MAX_BUFFER (SDW_PLAYBACK_MAX_PERIOD_SIZE * SDW_PLAYBACK_MAX_NUM_PERIODS)
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#define SDW_MIN_BUFFER SDW_MAX_BUFFER
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enum acp_config {
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ACP_CONFIG_0 = 0,
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ACP_CONFIG_1,
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ACP_CONFIG_2,
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ACP_CONFIG_3,
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ACP_CONFIG_4,
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ACP_CONFIG_5,
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ACP_CONFIG_6,
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ACP_CONFIG_7,
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ACP_CONFIG_8,
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ACP_CONFIG_9,
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ACP_CONFIG_10,
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ACP_CONFIG_11,
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ACP_CONFIG_12,
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ACP_CONFIG_13,
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ACP_CONFIG_14,
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ACP_CONFIG_15,
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};
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enum amd_sdw0_channel {
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ACP_SDW0_AUDIO0_TX = 0,
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ACP_SDW0_AUDIO1_TX,
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ACP_SDW0_AUDIO2_TX,
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ACP_SDW0_AUDIO0_RX,
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ACP_SDW0_AUDIO1_RX,
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ACP_SDW0_AUDIO2_RX,
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};
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enum amd_sdw1_channel {
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ACP_SDW1_AUDIO1_TX,
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ACP_SDW1_AUDIO1_RX,
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};
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struct pdm_stream_instance {
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u16 num_pages;
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u16 channels;
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dma_addr_t dma_addr;
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u64 bytescount;
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void __iomem *acp63_base;
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};
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struct pdm_dev_data {
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u32 pdm_irq;
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void __iomem *acp63_base;
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struct mutex *acp_lock;
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struct snd_pcm_substream *capture_stream;
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};
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struct sdw_dma_dev_data {
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void __iomem *acp_base;
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struct mutex *acp_lock; /* used to protect acp common register access */
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struct snd_pcm_substream *sdw0_dma_stream[ACP63_SDW0_DMA_MAX_STREAMS];
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struct snd_pcm_substream *sdw1_dma_stream[ACP63_SDW1_DMA_MAX_STREAMS];
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};
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struct acp_sdw_dma_stream {
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u16 num_pages;
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u16 channels;
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u32 stream_id;
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u32 instance;
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dma_addr_t dma_addr;
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u64 bytescount;
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};
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union acp_sdw_dma_count {
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struct {
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u32 low;
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u32 high;
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} bcount;
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u64 bytescount;
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};
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struct sdw_dma_ring_buf_reg {
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u32 reg_dma_size;
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u32 reg_fifo_addr;
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u32 reg_fifo_size;
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u32 reg_ring_buf_size;
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u32 reg_ring_buf_addr;
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u32 water_mark_size_reg;
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u32 pos_low_reg;
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u32 pos_high_reg;
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};
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/**
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* struct acp63_dev_data - acp pci driver context
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* @acp63_base: acp mmio base
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* @res: resource
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* @pdm_dev: ACP PDM controller platform device
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* @dmic_codec: platform device for DMIC Codec
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* sdw_dma_dev: platform device for SoundWire DMA controller
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* @mach_dev: platform device for machine driver to support ACP PDM/SoundWire configuration
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* @acp_lock: used to protect acp common registers
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* @info: SoundWire AMD information found in ACPI tables
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* @sdw: SoundWire context for all SoundWire manager instances
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* @machine: ACPI machines for SoundWire interface
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* @is_sdw_dev: flag set to true when any SoundWire manager instances are available
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* @is_pdm_dev: flag set to true when ACP PDM controller exists
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* @is_pdm_config: flat set to true when PDM configuration is selected from BIOS
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* @is_sdw_config: flag set to true when SDW configuration is selected from BIOS
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* @sdw_en_stat: flag set to true when any one of the SoundWire manager instance is enabled
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* @addr: pci ioremap address
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* @reg_range: ACP reigister range
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* @acp_rev: ACP PCI revision id
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* @sdw0-dma_intr_stat: DMA interrupt status array for SoundWire manager-SW0 instance
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* @sdw_dma_intr_stat: DMA interrupt status array for SoundWire manager-SW1 instance
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*/
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struct acp63_dev_data {
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void __iomem *acp63_base;
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struct resource *res;
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struct platform_device *pdm_dev;
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struct platform_device *dmic_codec_dev;
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struct platform_device *sdw_dma_dev;
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struct platform_device *mach_dev;
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struct mutex acp_lock; /* protect shared registers */
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struct sdw_amd_acpi_info info;
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/* sdw context allocated by SoundWire driver */
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struct sdw_amd_ctx *sdw;
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struct snd_soc_acpi_mach *machines;
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bool is_sdw_dev;
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bool is_pdm_dev;
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bool is_pdm_config;
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bool is_sdw_config;
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bool sdw_en_stat;
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u32 addr;
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u32 reg_range;
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u32 acp_rev;
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u16 sdw0_dma_intr_stat[ACP63_SDW0_DMA_MAX_STREAMS];
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u16 sdw1_dma_intr_stat[ACP63_SDW1_DMA_MAX_STREAMS];
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};
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int snd_amd_acp_find_config(struct pci_dev *pci);
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