160 lines
5.4 KiB
C
160 lines
5.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (C) 2023 Intel Corporation */
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#ifndef _ICE_ETHTOOL_H_
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#define _ICE_ETHTOOL_H_
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struct ice_phy_type_to_ethtool {
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u64 aq_link_speed;
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u8 link_mode;
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};
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struct ice_serdes_equalization_to_ethtool {
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int rx_equ_pre2;
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int rx_equ_pre1;
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int rx_equ_post1;
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int rx_equ_bflf;
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int rx_equ_bfhf;
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int rx_equ_drate;
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int rx_equ_ctle_gainhf;
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int rx_equ_ctle_gainlf;
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int rx_equ_ctle_gaindc;
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int rx_equ_ctle_bw;
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int rx_equ_dfe_gain;
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int rx_equ_dfe_gain_2;
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int rx_equ_dfe_2;
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int rx_equ_dfe_3;
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int rx_equ_dfe_4;
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int rx_equ_dfe_5;
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int rx_equ_dfe_6;
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int rx_equ_dfe_7;
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int rx_equ_dfe_8;
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int rx_equ_dfe_9;
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int rx_equ_dfe_10;
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int rx_equ_dfe_11;
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int rx_equ_dfe_12;
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int tx_equ_pre1;
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int tx_equ_pre3;
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int tx_equ_atten;
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int tx_equ_post1;
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int tx_equ_pre2;
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};
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struct ice_regdump_to_ethtool {
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/* A multilane port can have max 4 serdes */
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struct ice_serdes_equalization_to_ethtool equalization[4];
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};
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/* Port topology from lport i.e.
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* serdes mapping, pcsquad, macport, cage etc...
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*/
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struct ice_port_topology {
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u16 pcs_port;
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u16 primary_serdes_lane;
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u16 serdes_lane_count;
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u16 pcs_quad_select;
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};
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/* Macro to make PHY type to Ethtool link mode table entry.
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* The index is the PHY type.
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*/
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#define ICE_PHY_TYPE(LINK_SPEED, ETHTOOL_LINK_MODE) {\
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.aq_link_speed = ICE_AQ_LINK_SPEED_##LINK_SPEED, \
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.link_mode = ETHTOOL_LINK_MODE_##ETHTOOL_LINK_MODE##_BIT, \
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}
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/* Lookup table mapping PHY type low to link speed and Ethtool link modes.
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* Array index corresponds to HW PHY type bit, see
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* ice_adminq_cmd.h:ICE_PHY_TYPE_LOW_*.
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*/
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static const struct ice_phy_type_to_ethtool
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phy_type_low_lkup[] = {
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[0] = ICE_PHY_TYPE(100MB, 100baseT_Full),
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[1] = ICE_PHY_TYPE(100MB, 100baseT_Full),
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[2] = ICE_PHY_TYPE(1000MB, 1000baseT_Full),
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[3] = ICE_PHY_TYPE(1000MB, 1000baseX_Full),
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[4] = ICE_PHY_TYPE(1000MB, 1000baseX_Full),
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[5] = ICE_PHY_TYPE(1000MB, 1000baseKX_Full),
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[6] = ICE_PHY_TYPE(1000MB, 1000baseT_Full),
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[7] = ICE_PHY_TYPE(2500MB, 2500baseT_Full),
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[8] = ICE_PHY_TYPE(2500MB, 2500baseX_Full),
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[9] = ICE_PHY_TYPE(2500MB, 2500baseX_Full),
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[10] = ICE_PHY_TYPE(5GB, 5000baseT_Full),
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[11] = ICE_PHY_TYPE(5GB, 5000baseT_Full),
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[12] = ICE_PHY_TYPE(10GB, 10000baseT_Full),
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[13] = ICE_PHY_TYPE(10GB, 10000baseCR_Full),
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[14] = ICE_PHY_TYPE(10GB, 10000baseSR_Full),
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[15] = ICE_PHY_TYPE(10GB, 10000baseLR_Full),
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[16] = ICE_PHY_TYPE(10GB, 10000baseKR_Full),
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[17] = ICE_PHY_TYPE(10GB, 10000baseCR_Full),
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[18] = ICE_PHY_TYPE(10GB, 10000baseKR_Full),
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[19] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
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[20] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
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[21] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
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[22] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
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[23] = ICE_PHY_TYPE(25GB, 25000baseSR_Full),
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[24] = ICE_PHY_TYPE(25GB, 25000baseSR_Full),
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[25] = ICE_PHY_TYPE(25GB, 25000baseKR_Full),
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[26] = ICE_PHY_TYPE(25GB, 25000baseKR_Full),
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[27] = ICE_PHY_TYPE(25GB, 25000baseKR_Full),
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[28] = ICE_PHY_TYPE(25GB, 25000baseSR_Full),
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[29] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
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[30] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full),
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[31] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full),
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[32] = ICE_PHY_TYPE(40GB, 40000baseLR4_Full),
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[33] = ICE_PHY_TYPE(40GB, 40000baseKR4_Full),
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[34] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full),
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[35] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full),
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[36] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
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[37] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
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[38] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
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[39] = ICE_PHY_TYPE(50GB, 50000baseKR2_Full),
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[40] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
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[41] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
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[42] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
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[43] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
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[44] = ICE_PHY_TYPE(50GB, 50000baseCR_Full),
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[45] = ICE_PHY_TYPE(50GB, 50000baseSR_Full),
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[46] = ICE_PHY_TYPE(50GB, 50000baseLR_ER_FR_Full),
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[47] = ICE_PHY_TYPE(50GB, 50000baseLR_ER_FR_Full),
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[48] = ICE_PHY_TYPE(50GB, 50000baseKR_Full),
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[49] = ICE_PHY_TYPE(50GB, 50000baseSR_Full),
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[50] = ICE_PHY_TYPE(50GB, 50000baseCR_Full),
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[51] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
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[52] = ICE_PHY_TYPE(100GB, 100000baseSR4_Full),
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[53] = ICE_PHY_TYPE(100GB, 100000baseLR4_ER4_Full),
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[54] = ICE_PHY_TYPE(100GB, 100000baseKR4_Full),
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[55] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
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[56] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
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[57] = ICE_PHY_TYPE(100GB, 100000baseSR4_Full),
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[58] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
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[59] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
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[60] = ICE_PHY_TYPE(100GB, 100000baseKR4_Full),
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[61] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
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[62] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full),
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[63] = ICE_PHY_TYPE(100GB, 100000baseLR4_ER4_Full),
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};
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/* Lookup table mapping PHY type high to link speed and Ethtool link modes.
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* Array index corresponds to HW PHY type bit, see
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* ice_adminq_cmd.h:ICE_PHY_TYPE_HIGH_*
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*/
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static const struct ice_phy_type_to_ethtool
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phy_type_high_lkup[] = {
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[0] = ICE_PHY_TYPE(100GB, 100000baseKR2_Full),
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[1] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full),
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[2] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
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[3] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full),
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[4] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
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[5] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full),
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[6] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full),
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[7] = ICE_PHY_TYPE(200GB, 200000baseLR4_ER4_FR4_Full),
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[8] = ICE_PHY_TYPE(200GB, 200000baseLR4_ER4_FR4_Full),
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[9] = ICE_PHY_TYPE(200GB, 200000baseDR4_Full),
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[10] = ICE_PHY_TYPE(200GB, 200000baseKR4_Full),
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[11] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full),
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[12] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full),
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};
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#endif /* !_ICE_ETHTOOL_H_ */
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