144 lines
5.8 KiB
C
144 lines
5.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/* Copyright (c) 2024 Hisilicon Limited. */
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#ifndef __HBG_REG_H
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#define __HBG_REG_H
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/* DEV SPEC */
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#define HBG_REG_SPEC_VALID_ADDR 0x0000
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#define HBG_REG_EVENT_REQ_ADDR 0x0004
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#define HBG_REG_MAC_ID_ADDR 0x0008
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#define HBG_REG_PHY_ID_ADDR 0x000C
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#define HBG_REG_MAC_ADDR_ADDR 0x0010
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#define HBG_REG_MDIO_FREQ_ADDR 0x0024
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#define HBG_REG_MAX_MTU_ADDR 0x0028
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#define HBG_REG_MIN_MTU_ADDR 0x002C
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#define HBG_REG_TX_FIFO_NUM_ADDR 0x0030
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#define HBG_REG_RX_FIFO_NUM_ADDR 0x0034
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#define HBG_REG_VLAN_LAYERS_ADDR 0x0038
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/* MDIO */
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#define HBG_REG_MDIO_BASE 0x8000
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#define HBG_REG_MDIO_COMMAND_ADDR (HBG_REG_MDIO_BASE + 0x0000)
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#define HBG_REG_MDIO_COMMAND_CLK_SEL_EXP_B BIT(17)
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#define HBG_REG_MDIO_COMMAND_AUTO_SCAN_B BIT(16)
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#define HBG_REG_MDIO_COMMAND_CLK_SEL_B BIT(15)
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#define HBG_REG_MDIO_COMMAND_START_B BIT(14)
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#define HBG_REG_MDIO_COMMAND_ST_M GENMASK(13, 12)
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#define HBG_REG_MDIO_COMMAND_OP_M GENMASK(11, 10)
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#define HBG_REG_MDIO_COMMAND_PRTAD_M GENMASK(9, 5)
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#define HBG_REG_MDIO_COMMAND_DEVAD_M GENMASK(4, 0)
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#define HBG_REG_MDIO_WDATA_ADDR (HBG_REG_MDIO_BASE + 0x0008)
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#define HBG_REG_MDIO_WDATA_M GENMASK(15, 0)
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#define HBG_REG_MDIO_RDATA_ADDR (HBG_REG_MDIO_BASE + 0x000C)
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#define HBG_REG_MDIO_STA_ADDR (HBG_REG_MDIO_BASE + 0x0010)
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/* GMAC */
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#define HBG_REG_SGMII_BASE 0x10000
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#define HBG_REG_DUPLEX_TYPE_ADDR (HBG_REG_SGMII_BASE + 0x0008)
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#define HBG_REG_DUPLEX_B BIT(0)
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#define HBG_REG_MAX_FRAME_SIZE_ADDR (HBG_REG_SGMII_BASE + 0x003C)
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#define HBG_REG_PORT_MODE_ADDR (HBG_REG_SGMII_BASE + 0x0040)
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#define HBG_REG_PORT_MODE_M GENMASK(3, 0)
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#define HBG_REG_PORT_ENABLE_ADDR (HBG_REG_SGMII_BASE + 0x0044)
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#define HBG_REG_PORT_ENABLE_RX_B BIT(1)
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#define HBG_REG_PORT_ENABLE_TX_B BIT(2)
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#define HBG_REG_TRANSMIT_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x0060)
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#define HBG_REG_TRANSMIT_CTRL_PAD_EN_B BIT(7)
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#define HBG_REG_TRANSMIT_CTRL_CRC_ADD_B BIT(6)
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#define HBG_REG_TRANSMIT_CTRL_AN_EN_B BIT(5)
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#define HBG_REG_CF_CRC_STRIP_ADDR (HBG_REG_SGMII_BASE + 0x01B0)
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#define HBG_REG_CF_CRC_STRIP_B BIT(0)
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#define HBG_REG_MODE_CHANGE_EN_ADDR (HBG_REG_SGMII_BASE + 0x01B4)
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#define HBG_REG_MODE_CHANGE_EN_B BIT(0)
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#define HBG_REG_RECV_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x01E0)
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#define HBG_REG_RECV_CTRL_STRIP_PAD_EN_B BIT(3)
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#define HBG_REG_STATION_ADDR_LOW_2_ADDR (HBG_REG_SGMII_BASE + 0x0210)
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#define HBG_REG_STATION_ADDR_HIGH_2_ADDR (HBG_REG_SGMII_BASE + 0x0214)
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/* PCU */
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#define HBG_REG_CF_INTRPT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x042C)
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#define HBG_INT_MSK_WE_ERR_B BIT(31)
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#define HBG_INT_MSK_RBREQ_ERR_B BIT(30)
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#define HBG_INT_MSK_MAC_FIFO_ERR_B BIT(29)
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#define HBG_INT_MSK_RX_AHB_ERR_B BIT(28)
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#define HBG_INT_MSK_RX_DROP_B BIT(26)
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#define HBG_INT_MSK_TX_DROP_B BIT(25)
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#define HBG_INT_MSK_TXCFG_AVL_B BIT(24)
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#define HBG_INT_MSK_REL_BUF_ERR_B BIT(23)
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#define HBG_INT_MSK_RX_BUF_AVL_B BIT(22)
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#define HBG_INT_MSK_TX_AHB_ERR_B BIT(21)
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#define HBG_INT_MSK_SRAM_PARITY_ERR_B BIT(20)
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#define HBG_INT_MSK_MAC_APP_TX_FIFO_ERR_B BIT(19)
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#define HBG_INT_MSK_MAC_APP_RX_FIFO_ERR_B BIT(18)
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#define HBG_INT_MSK_MAC_PCS_TX_FIFO_ERR_B BIT(17)
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#define HBG_INT_MSK_MAC_PCS_RX_FIFO_ERR_B BIT(16)
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#define HBG_INT_MSK_MAC_MII_FIFO_ERR_B BIT(15)
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#define HBG_INT_MSK_TX_B BIT(1) /* just used in driver */
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#define HBG_INT_MSK_RX_B BIT(0) /* just used in driver */
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#define HBG_REG_CF_INTRPT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x0434)
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#define HBG_REG_CF_INTRPT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x0438)
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#define HBG_REG_MAX_FRAME_LEN_ADDR (HBG_REG_SGMII_BASE + 0x0444)
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#define HBG_REG_MAX_FRAME_LEN_M GENMASK(15, 0)
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#define HBG_REG_CF_CFF_DATA_NUM_ADDR (HBG_REG_SGMII_BASE + 0x045C)
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#define HBG_REG_CF_CFF_DATA_NUM_ADDR_TX_M GENMASK(8, 0)
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#define HBG_REG_CF_CFF_DATA_NUM_ADDR_RX_M GENMASK(24, 16)
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#define HBG_REG_TX_CFF_ADDR_0_ADDR (HBG_REG_SGMII_BASE + 0x0488)
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#define HBG_REG_TX_CFF_ADDR_1_ADDR (HBG_REG_SGMII_BASE + 0x048C)
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#define HBG_REG_TX_CFF_ADDR_2_ADDR (HBG_REG_SGMII_BASE + 0x0490)
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#define HBG_REG_TX_CFF_ADDR_3_ADDR (HBG_REG_SGMII_BASE + 0x0494)
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#define HBG_REG_RX_CFF_ADDR_ADDR (HBG_REG_SGMII_BASE + 0x04A0)
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#define HBG_REG_RX_BUF_SIZE_ADDR (HBG_REG_SGMII_BASE + 0x04E4)
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#define HBG_REG_RX_BUF_SIZE_M GENMASK(15, 0)
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#define HBG_REG_BUS_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x04E8)
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#define HBG_REG_BUS_CTRL_ENDIAN_M GENMASK(2, 1)
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#define HBG_REG_RX_CTRL_ADDR (HBG_REG_SGMII_BASE + 0x04F0)
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#define HBG_REG_RX_CTRL_RXBUF_1ST_SKIP_SIZE_M GENMASK(31, 28)
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#define HBG_REG_RX_CTRL_TIME_INF_EN_B BIT(23)
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#define HBG_REG_RX_CTRL_RX_ALIGN_NUM_M GENMASK(18, 17)
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#define HBG_REG_RX_CTRL_PORT_NUM GENMASK(16, 13)
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#define HBG_REG_RX_CTRL_RX_GET_ADDR_MODE_B BIT(12)
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#define HBG_REG_RX_CTRL_RXBUF_1ST_SKIP_SIZE2_M GENMASK(3, 0)
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#define HBG_REG_RX_PKT_MODE_ADDR (HBG_REG_SGMII_BASE + 0x04F4)
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#define HBG_REG_RX_PKT_MODE_PARSE_MODE_M GENMASK(22, 21)
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#define HBG_REG_CF_IND_TXINT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x0694)
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#define HBG_REG_IND_INTR_MASK_B BIT(0)
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#define HBG_REG_CF_IND_TXINT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x0698)
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#define HBG_REG_CF_IND_TXINT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x069C)
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#define HBG_REG_CF_IND_RXINT_MSK_ADDR (HBG_REG_SGMII_BASE + 0x06a0)
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#define HBG_REG_CF_IND_RXINT_STAT_ADDR (HBG_REG_SGMII_BASE + 0x06a4)
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#define HBG_REG_CF_IND_RXINT_CLR_ADDR (HBG_REG_SGMII_BASE + 0x06a8)
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enum hbg_port_mode {
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/* 0x0 ~ 0x5 are reserved */
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HBG_PORT_MODE_SGMII_10M = 0x6,
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HBG_PORT_MODE_SGMII_100M = 0x7,
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HBG_PORT_MODE_SGMII_1000M = 0x8,
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};
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struct hbg_tx_desc {
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u32 word0;
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u32 word1;
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u32 word2; /* pkt_addr */
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u32 word3; /* clear_addr */
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};
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#define HBG_TX_DESC_W0_IP_OFF_M GENMASK(30, 26)
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#define HBG_TX_DESC_W0_l3_CS_B BIT(2)
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#define HBG_TX_DESC_W0_WB_B BIT(1)
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#define HBG_TX_DESC_W0_l4_CS_B BIT(0)
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#define HBG_TX_DESC_W1_SEND_LEN_M GENMASK(19, 4)
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struct hbg_rx_desc {
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u32 word0;
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u32 word1; /* tag */
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u32 word2;
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u32 word3;
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u32 word4;
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u32 word5;
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};
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#define HBG_RX_DESC_W2_PKT_LEN_M GENMASK(31, 16)
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#endif
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