156 lines
4.9 KiB
C
156 lines
4.9 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/*
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* This header file defines the register offsets and bit fields
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* of ENETC4 PF and VFs. Note that the same registers as ENETC
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* version 1.0 are defined in the enetc_hw.h file.
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*
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* Copyright 2024 NXP
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*/
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#ifndef __ENETC4_HW_H_
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#define __ENETC4_HW_H_
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#define NXP_ENETC_VENDOR_ID 0x1131
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#define NXP_ENETC_PF_DEV_ID 0xe101
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/***************************ENETC port registers**************************/
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#define ENETC4_ECAPR0 0x0
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#define ECAPR0_RFS BIT(2)
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#define ECAPR0_TSD BIT(5)
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#define ECAPR0_RSS BIT(8)
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#define ECAPR0_RSC BIT(9)
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#define ECAPR0_LSO BIT(10)
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#define ECAPR0_WO BIT(13)
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#define ENETC4_ECAPR1 0x4
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#define ECAPR1_NUM_TCS GENMASK(6, 4)
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#define ECAPR1_NUM_MCH GENMASK(9, 8)
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#define ECAPR1_NUM_UCH GENMASK(11, 10)
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#define ECAPR1_NUM_MSIX GENMASK(22, 12)
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#define ECAPR1_NUM_VSI GENMASK(27, 24)
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#define ECAPR1_NUM_IPV BIT(31)
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#define ENETC4_ECAPR2 0x8
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#define ECAPR2_NUM_TX_BDR GENMASK(9, 0)
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#define ECAPR2_NUM_RX_BDR GENMASK(25, 16)
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#define ENETC4_PMR 0x10
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#define PMR_SI_EN(a) BIT((16 + (a)))
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/* Port Pause ON/OFF threshold register */
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#define ENETC4_PPAUONTR 0x108
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#define ENETC4_PPAUOFFTR 0x10c
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/* Port Station interface promiscuous MAC mode register */
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#define ENETC4_PSIPMMR 0x200
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#define PSIPMMR_SI_MAC_UP(a) BIT(a) /* a = SI index */
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#define PSIPMMR_SI_MAC_MP(a) BIT((a) + 16)
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/* Port Station interface promiscuous VLAN mode register */
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#define ENETC4_PSIPVMR 0x204
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/* Port RSS key register n. n = 0,1,2,...,9 */
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#define ENETC4_PRSSKR(n) ((n) * 0x4 + 0x250)
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/* Port station interface MAC address filtering capability register */
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#define ENETC4_PSIMAFCAPR 0x280
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#define PSIMAFCAPR_NUM_MAC_AFTE GENMASK(11, 0)
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/* Port station interface VLAN filtering capability register */
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#define ENETC4_PSIVLANFCAPR 0x2c0
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#define PSIVLANFCAPR_NUM_VLAN_FTE GENMASK(11, 0)
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/* Port station interface VLAN filtering mode register */
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#define ENETC4_PSIVLANFMR 0x2c4
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#define PSIVLANFMR_VS BIT(0)
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/* Port Station interface a primary MAC address registers */
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#define ENETC4_PSIPMAR0(a) ((a) * 0x80 + 0x2000)
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#define ENETC4_PSIPMAR1(a) ((a) * 0x80 + 0x2004)
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/* Port station interface a configuration register 0/2 */
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#define ENETC4_PSICFGR0(a) ((a) * 0x80 + 0x2010)
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#define PSICFGR0_VASE BIT(13)
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#define PSICFGR0_ASE BIT(15)
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#define PSICFGR0_ANTI_SPOOFING (PSICFGR0_VASE | PSICFGR0_ASE)
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#define ENETC4_PSICFGR2(a) ((a) * 0x80 + 0x2018)
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#define PSICFGR2_NUM_MSIX GENMASK(5, 0)
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#define ENETC4_PMCAPR 0x4004
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#define PMCAPR_HD BIT(8)
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#define PMCAPR_FP GENMASK(10, 9)
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/* Port configuration register */
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#define ENETC4_PCR 0x4010
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#define PCR_HDR_FMT BIT(0)
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#define PCR_L2DOSE BIT(4)
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#define PCR_TIMER_CS BIT(8)
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#define PCR_PSPEED GENMASK(29, 16)
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#define PCR_PSPEED_VAL(speed) (((speed) / 10 - 1) << 16)
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/* Port MAC address register 0/1 */
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#define ENETC4_PMAR0 0x4020
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#define ENETC4_PMAR1 0x4024
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/* Port operational register */
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#define ENETC4_POR 0x4100
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/* Port traffic class a transmit maximum SDU register */
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#define ENETC4_PTCTMSDUR(a) ((a) * 0x20 + 0x4208)
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#define PTCTMSDUR_MAXSDU GENMASK(15, 0)
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#define PTCTMSDUR_SDU_TYPE GENMASK(17, 16)
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#define SDU_TYPE_PPDU 0
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#define SDU_TYPE_MPDU 1
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#define SDU_TYPE_MSDU 2
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#define ENETC4_PMAC_OFFSET 0x400
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#define ENETC4_PM_CMD_CFG(mac) (0x5008 + (mac) * 0x400)
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#define PM_CMD_CFG_TX_EN BIT(0)
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#define PM_CMD_CFG_RX_EN BIT(1)
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#define PM_CMD_CFG_PAUSE_FWD BIT(7)
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#define PM_CMD_CFG_PAUSE_IGN BIT(8)
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#define PM_CMD_CFG_TX_ADDR_INS BIT(9)
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#define PM_CMD_CFG_LOOP_EN BIT(10)
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#define PM_CMD_CFG_LPBK_MODE GENMASK(12, 11)
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#define LPBCK_MODE_EXT_TX_CLK 0
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#define LPBCK_MODE_MAC_LEVEL 1
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#define LPBCK_MODE_INT_TX_CLK 2
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#define PM_CMD_CFG_CNT_FRM_EN BIT(13)
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#define PM_CMD_CFG_TXP BIT(15)
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#define PM_CMD_CFG_SEND_IDLE BIT(16)
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#define PM_CMD_CFG_HD_FCEN BIT(18)
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#define PM_CMD_CFG_SFD BIT(21)
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#define PM_CMD_CFG_TX_FLUSH BIT(22)
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#define PM_CMD_CFG_TX_LOWP_EN BIT(23)
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#define PM_CMD_CFG_RX_LOWP_EMPTY BIT(24)
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#define PM_CMD_CFG_SWR BIT(26)
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#define PM_CMD_CFG_TS_MODE BIT(30)
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#define PM_CMD_CFG_MG BIT(31)
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/* Port MAC 0/1 Maximum Frame Length Register */
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#define ENETC4_PM_MAXFRM(mac) (0x5014 + (mac) * 0x400)
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/* Port MAC 0/1 Pause Quanta Register */
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#define ENETC4_PM_PAUSE_QUANTA(mac) (0x5054 + (mac) * 0x400)
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/* Port MAC 0/1 Pause Quanta Threshold Register */
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#define ENETC4_PM_PAUSE_THRESH(mac) (0x5064 + (mac) * 0x400)
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/* Port MAC 0 Interface Mode Control Register */
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#define ENETC4_PM_IF_MODE(mac) (0x5300 + (mac) * 0x400)
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#define PM_IF_MODE_IFMODE GENMASK(2, 0)
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#define IFMODE_XGMII 0
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#define IFMODE_RMII 3
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#define IFMODE_RGMII 4
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#define IFMODE_SGMII 5
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#define PM_IF_MODE_REVMII BIT(3)
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#define PM_IF_MODE_M10 BIT(4)
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#define PM_IF_MODE_HD BIT(6)
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#define PM_IF_MODE_SSP GENMASK(14, 13)
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#define SSP_100M 0
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#define SSP_10M 1
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#define SSP_1G 2
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#define PM_IF_MODE_ENA BIT(15)
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#endif
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