40 lines
962 B
C
40 lines
962 B
C
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef _XE_GT_TOPOLOGY_H_
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#define _XE_GT_TOPOLOGY_H_
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#include "xe_gt_types.h"
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/*
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* Loop over each DSS with the bit is 1 in geometry or compute mask
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* @dss: iterated DSS bit from the DSS mask
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* @gt: GT structure
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*/
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#define for_each_dss(dss, gt) \
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for_each_or_bit((dss), \
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(gt)->fuse_topo.g_dss_mask, \
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(gt)->fuse_topo.c_dss_mask, \
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XE_MAX_DSS_FUSE_BITS)
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struct drm_printer;
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void xe_gt_topology_init(struct xe_gt *gt);
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void xe_gt_topology_dump(struct xe_gt *gt, struct drm_printer *p);
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unsigned int
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xe_dss_mask_group_ffs(const xe_dss_mask_t mask, int groupsize, int groupnum);
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bool xe_dss_mask_empty(const xe_dss_mask_t mask);
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bool
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xe_gt_topology_has_dss_in_quadrant(struct xe_gt *gt, int quad);
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bool xe_gt_has_geometry_dss(struct xe_gt *gt, unsigned int dss);
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bool xe_gt_has_compute_dss(struct xe_gt *gt, unsigned int dss);
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#endif /* _XE_GT_TOPOLOGY_H_ */
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