674 lines
12 KiB
Plaintext
674 lines
12 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
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*
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* DTS for SolidRun CN9132 Clearfog.
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*
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include "cn9130.dtsi"
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#include "cn9132-sr-cex7.dtsi"
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/ {
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model = "SolidRun CN9132 Clearfog";
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compatible = "solidrun,cn9132-clearfog",
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"solidrun,cn9132-sr-cex7", "marvell,cn9130";
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aliases {
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ethernet1 = &cp0_eth2;
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ethernet2 = &cp0_eth0;
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ethernet3 = &cp2_eth0;
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ethernet4 = &cp1_eth0;
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i2c7 = &carrier_mpcie_i2c;
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i2c8 = &carrier_ptp_i2c;
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mmc1 = &cp0_sdhci0;
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_wake0_pins>;
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button-0 {
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label = "SW2";
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gpios = <&cp1_gpio2 8 GPIO_ACTIVE_LOW>;
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linux,can-disable;
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linux,code = <BTN_2>;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_batlow_pins &cp2_rsvd4_pins>;
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/* LED11 */
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led-io-0 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_DISK;
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function-enumerator = <0>;
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default-state = "off";
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gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
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};
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/* LED12 */
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led-io-1 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_DISK;
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function-enumerator = <1>;
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default-state = "off";
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gpios = <&cp2_gpio1 4 GPIO_ACTIVE_HIGH>;
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};
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};
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/* CON4 W_DISABLE1/W_DISABLE2 */
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rfkill-m2-wlan {
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compatible = "rfkill-gpio";
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label = "m.2 wlan (CON4)";
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radio-type = "wlan";
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_10g_phy_rst_01_pins>;
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/* rfkill-gpio inverts internally */
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shutdown-gpios = <&cp1_gpio2 11 GPIO_ACTIVE_HIGH>;
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};
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/* CON5 W_DISABLE1/W_DISABLE2 */
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rfkill-m2-wlan {
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compatible = "rfkill-gpio";
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label = "m.2 wlan (CON5)";
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radio-type = "wlan";
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_10g_phy_rst_23_pins>;
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/* rfkill-gpio inverts internally */
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shutdown-gpios = <&cp1_gpio2 10 GPIO_ACTIVE_HIGH>;
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};
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/* J21 W_DISABLE1 */
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rfkill-m2-wwan {
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compatible = "rfkill-gpio";
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label = "m.2 wwan (J21)";
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radio-type = "wwan";
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pinctrl-names = "default";
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pinctrl-0 = <&cp2_rsvd3_pins>;
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/* rfkill-gpio inverts internally */
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shutdown-gpios = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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/* J21 W_DISABLE1 */
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rfkill-m2-gnss {
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compatible = "rfkill-gpio";
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label = "m.2 gnss (J21)";
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radio-type = "gps";
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pinctrl-names = "default";
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pinctrl-0 = <&cp2_rsvd8_pins>;
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/* rfkill-gpio inverts internally */
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shutdown-gpios = <&cp2_gpio1 8 GPIO_ACTIVE_HIGH>;
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};
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/* J14 W_DISABLE */
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rfkill-mpcie-wlan {
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compatible = "rfkill-gpio";
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label = "mpcie wlan (J14)";
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radio-type = "wlan";
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pinctrl-names = "default";
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pinctrl-0 = <&cp2_rsvd2_pins>;
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/* rfkill-gpio inverts internally */
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shutdown-gpios = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
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};
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sfp: sfp {
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compatible = "sff,sfp";
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i2c-bus = <&com_10g_sfp_i2c0>;
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pinctrl-names = "default";
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pinctrl-0 = <&com_10g_int0_pins>;
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mod-def0-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_LOW>;
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maximum-power-milliwatt = <2000>;
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};
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};
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&com_smbus {
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/* This bus is also routed to STM32 BMC Microcontroller (U2) */
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power-sensor@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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#io-channel-cells = <1>;
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label = "vdd_12v0";
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shunt-resistor = <2000>;
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};
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adc@48 {
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compatible = "ti,tla2021";
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reg = <0x48>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* supplied by chaoskey hardware noise generator circuit */
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channel@0 {
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reg = <0>;
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};
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};
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};
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&cp0_eth_phy0 {
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/*
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* Configure LEDs default behaviour:
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* - LED[0]: link is 1000Mbps: On (yellow): 0111
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* - LED[1]: link/activity: On/Blink (green): 0001
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* - LED[2]: Off (green): 1000
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*/
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marvell,reg-init = <3 16 0xf000 0x0817>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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/* link */
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reg = <0>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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led@1 {
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/* act */
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reg = <1>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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led@2 {
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/* 1000 */
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reg = <2>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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/* SRDS #4 - 10GE */
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&cp0_eth0 {
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phys = <&cp0_comphy4 0>;
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phy-mode = "10gbase-r";
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managed = "in-band-status";
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sfp = <&sfp>;
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status = "okay";
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};
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&cp0_eth2 {
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phy-mode = "2500base-x";
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phys = <&cp0_comphy5 2>;
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status = "okay";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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&cp0_i2c1 {
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/*
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* Both COM and Carrier Board have a PCA9547 i2c mux at 0x77.
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* Describe them as a single device merging each child bus.
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*/
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i2c-mux@77 {
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i2c@0 {
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/* Routed to Full PCIe (J4) */
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};
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i2c@1 {
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/* Routed to USB Hub (U29) */
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};
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i2c@2 {
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/* Routed to M.2 (CON4) */
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};
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i2c@3 {
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/* Routed to M.2 (CON5) */
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};
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i2c@4 {
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/* Routed to M.2 (J21) */
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};
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carrier_mpcie_i2c: i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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/* Routed to mini-PCIe (J14) */
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};
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carrier_ptp_i2c: i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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/* Routed to various optional PTP related components */
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};
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};
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};
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&cp0_mdio {
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ethernet-switch@4 {
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compatible = "marvell,mv88e6085";
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reg = <4>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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sw_phy1: ethernet-phy@1 {
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reg = <0x11>;
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};
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sw_phy2: ethernet-phy@2 {
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reg = <0x12>;
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};
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sw_phy3: ethernet-phy@3 {
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reg = <0x13>;
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};
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sw_phy4: ethernet-phy@4 {
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reg = <0x14>;
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};
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};
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&sw_phy1>;
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phy-mode = "internal";
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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ethernet-port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&sw_phy2>;
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phy-mode = "internal";
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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ethernet-port@3 {
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reg = <3>;
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label = "lan3";
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phy-handle = <&sw_phy3>;
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phy-mode = "internal";
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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ethernet-port@4 {
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reg = <4>;
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label = "lan4";
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phy-handle = <&sw_phy4>;
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phy-mode = "internal";
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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ethernet-port@5 {
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reg = <5>;
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label = "cpu";
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ethernet = <&cp0_eth2>;
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phy-mode = "2500base-x";
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fixed-link {
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|
speed = <2500>;
|
||
|
|
full-duplex;
|
||
|
|
pause;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/* SRDS #0,#1,#2,#3 - PCIe */
|
||
|
|
&cp0_pcie0 {
|
||
|
|
num-lanes = <4>;
|
||
|
|
phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&cp0_pinctrl {
|
||
|
|
/*
|
||
|
|
* configure unused gpios exposed via pin headers:
|
||
|
|
* - J7-10: PWRBTN
|
||
|
|
*/
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&cp0_pwrbtn_pins>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* microSD */
|
||
|
|
&cp0_sdhci0 {
|
||
|
|
pinctrl-0 = <&cp0_mmc0_pins>, <&cp0_mmc0_cd_pins>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
bus-width = <4>;
|
||
|
|
no-1-8-v;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&cp0_spi1 {
|
||
|
|
/* add CS1 */
|
||
|
|
pinctrl-0 = <&cp0_spi1_pins>, <&cp0_spi1_cs1_pins>;
|
||
|
|
|
||
|
|
flash@1 {
|
||
|
|
compatible = "jedec,spi-nor";
|
||
|
|
reg = <1>;
|
||
|
|
/* read command supports max. 50MHz */
|
||
|
|
spi-max-frequency = <50000000>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/* J38 */
|
||
|
|
&cp0_uart2 {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&cp0_uart2_pins>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&cp0_utmi {
|
||
|
|
/* M.2 "CON5" swaps D+/D- */
|
||
|
|
swap-dx-lanes = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&cp1_ethernet {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* SRDS #2 - 5GE */
|
||
|
|
&cp1_eth0 {
|
||
|
|
phys = <&cp1_comphy2 0>;
|
||
|
|
phy-mode = "5gbase-r";
|
||
|
|
phy = <&cp1_eth_phy0>;
|
||
|
|
managed = "in-band-status";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* SRDS #0,#1 - PCIe */
|
||
|
|
&cp1_pcie0 {
|
||
|
|
num-lanes = <2>;
|
||
|
|
phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* SRDS #4 - PCIe */
|
||
|
|
&cp1_pcie1 {
|
||
|
|
num-lanes = <1>;
|
||
|
|
phys = <&cp1_comphy4 1>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* SRDS #5 - PCIe */
|
||
|
|
&cp1_pcie2 {
|
||
|
|
num-lanes = <1>;
|
||
|
|
phys = <&cp1_comphy5 2>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&cp1_pinctrl {
|
||
|
|
/*
|
||
|
|
* configure unused gpios exposed via pin headers:
|
||
|
|
* - J7-8: RSVD16
|
||
|
|
* - J7-10: THRM
|
||
|
|
* - J10-1: WAKE1
|
||
|
|
* - J10-2: SATA_ACT
|
||
|
|
* - J10-8: THERMTRIP
|
||
|
|
*/
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&cp1_rsvd16_pins &cp1_sata_act_pins &cp1_thrm_irq_pins>,
|
||
|
|
<&cp1_thrm_trip_pins &cp1_wake1_pins>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* SRDS #3 - SATA */
|
||
|
|
&cp1_sata0 {
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
/* only port 1 is available */
|
||
|
|
/delete-node/ sata-port@0;
|
||
|
|
|
||
|
|
sata-port@1 {
|
||
|
|
phys = <&cp1_comphy3 1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&cp1_utmi {
|
||
|
|
/* M.2 "CON4" swaps D+/D- */
|
||
|
|
swap-dx-lanes = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&cp1_xmdio {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&cp1_xmdio_pins>;
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
cp1_eth_phy0: ethernet-phy@8 {
|
||
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
||
|
|
reg = <8>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&com_10g_int1_pins>;
|
||
|
|
interrupt-parent = <&cp1_gpio2>;
|
||
|
|
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||
|
|
|
||
|
|
leds {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
led@1 {
|
||
|
|
reg = <1>;
|
||
|
|
color = <LED_COLOR_ID_YELLOW>;
|
||
|
|
function = LED_FUNCTION_LAN;
|
||
|
|
default-state = "keep";
|
||
|
|
};
|
||
|
|
|
||
|
|
led@2 {
|
||
|
|
reg = <2>;
|
||
|
|
color = <LED_COLOR_ID_GREEN>;
|
||
|
|
function = LED_FUNCTION_LAN;
|
||
|
|
default-state = "keep";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&cp2_ethernet {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* SRDS #2 - 5GE */
|
||
|
|
&cp2_eth0 {
|
||
|
|
phys = <&cp2_comphy2 0>;
|
||
|
|
phy-mode = "5gbase-r";
|
||
|
|
phy = <&cp2_eth_phy0>;
|
||
|
|
managed = "in-band-status";
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&cp2_gpio1 {
|
||
|
|
pinctrl-names= "default";
|
||
|
|
pinctrl-0 = <&cp2_rsvd9_pins>;
|
||
|
|
|
||
|
|
/* J21 */
|
||
|
|
m2-wwan-reset-hog {
|
||
|
|
gpio-hog;
|
||
|
|
gpios = <9 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
|
||
|
|
output-low;
|
||
|
|
line-name = "m2-wwan-reset";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/* SRDS #0 - PCIe */
|
||
|
|
&cp2_pcie0 {
|
||
|
|
num-lanes = <1>;
|
||
|
|
phys = <&cp2_comphy0 0>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* SRDS #4 - PCIe */
|
||
|
|
&cp2_pcie1 {
|
||
|
|
num-lanes = <1>;
|
||
|
|
phys = <&cp2_comphy4 1>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
/* SRDS #5 - PCIe */
|
||
|
|
&cp2_pcie2 {
|
||
|
|
num-lanes = <1>;
|
||
|
|
phys = <&cp2_comphy5 2>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&cp2_pinctrl {
|
||
|
|
/*
|
||
|
|
* configure unused gpios exposed via pin headers:
|
||
|
|
* - J7-1: RSVD10
|
||
|
|
* - J7-3: RSVD11
|
||
|
|
* - J7-5: RSVD56
|
||
|
|
* - J7-6: RSVD7
|
||
|
|
* - J7-7: RSVD27
|
||
|
|
* - J10-3: RSVD31
|
||
|
|
* - J10-5: RSVD5
|
||
|
|
* - J10-6: RSVD32
|
||
|
|
* - J10-7: RSVD0
|
||
|
|
* - J10-9: RSVD1
|
||
|
|
*/
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&cp2_rsvd0_pins &cp2_rsvd1_pins &cp2_rsvd5_pins>,
|
||
|
|
<&cp2_rsvd7_pins &cp2_rsvd10_pins &cp2_rsvd11_pins>,
|
||
|
|
<&cp2_rsvd27_pins &cp2_rsvd31_pins &cp2_rsvd32_pins>,
|
||
|
|
<&cp2_rsvd56_pins>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* SRDS #3 - SATA */
|
||
|
|
&cp2_sata0 {
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
/* only port 1 is available */
|
||
|
|
/delete-node/ sata-port@0;
|
||
|
|
|
||
|
|
sata-port@1 {
|
||
|
|
phys = <&cp2_comphy3 1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&cp2_xmdio {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&cp2_xmdio_pins>;
|
||
|
|
status = "okay";
|
||
|
|
|
||
|
|
cp2_eth_phy0: ethernet-phy@8 {
|
||
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
||
|
|
reg = <8>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&com_10g_int2_pins>;
|
||
|
|
interrupt-parent = <&cp2_gpio2>;
|
||
|
|
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||
|
|
|
||
|
|
leds {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
led@1 {
|
||
|
|
reg = <1>;
|
||
|
|
color = <LED_COLOR_ID_YELLOW>;
|
||
|
|
function = LED_FUNCTION_LAN;
|
||
|
|
default-state = "keep";
|
||
|
|
};
|
||
|
|
|
||
|
|
led@2 {
|
||
|
|
reg = <2>;
|
||
|
|
color = <LED_COLOR_ID_GREEN>;
|
||
|
|
function = LED_FUNCTION_LAN;
|
||
|
|
default-state = "keep";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|