42 lines
1.2 KiB
Plaintext
42 lines
1.2 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2024 NXP
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* Richard Zhu <hongxing.zhu@nxp.com>
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*/
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&hsio_subsys {
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phyx1_lpcg: clock-controller@5f090000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5f090000 0x10000>;
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clocks = <&hsio_refb_clk>, <&hsio_per_clk>,
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<&hsio_per_clk>, <&hsio_per_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>;
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clock-output-names = "hsio_phyx1_pclk",
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"hsio_phyx1_epcs_tx_clk",
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"hsio_phyx1_epcs_rx_clk",
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"hsio_phyx1_apb_clk";
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power-domains = <&pd IMX_SC_R_SERDES_1>;
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};
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hsio_phy: phy@5f1a0000 {
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compatible = "fsl,imx8qxp-hsio";
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reg = <0x5f1a0000 0x10000>,
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<0x5f120000 0x10000>,
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<0x5f140000 0x10000>,
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<0x5f160000 0x10000>;
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reg-names = "reg", "phy", "ctrl", "misc";
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clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>,
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<&phyx1_lpcg IMX_LPCG_CLK_1>,
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<&phyx1_crr1_lpcg IMX_LPCG_CLK_4>,
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<&pcieb_crr3_lpcg IMX_LPCG_CLK_4>,
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<&misc_crr5_lpcg IMX_LPCG_CLK_4>;
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clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr",
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"misc_crr";
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#phy-cells = <3>;
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power-domains = <&pd IMX_SC_R_SERDES_1>;
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status = "disabled";
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};
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};
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