210 lines
6.4 KiB
Plaintext
210 lines
6.4 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2024 NXP
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* Richard Zhu <hongxing.zhu@nxp.com>
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*/
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&hsio_subsys {
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compatible = "simple-bus";
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ranges = <0x5f000000 0x0 0x5f000000 0x01000000>,
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<0x40000000 0x0 0x60000000 0x10000000>,
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<0x80000000 0x0 0x70000000 0x10000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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pciea: pcie@5f000000 {
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compatible = "fsl,imx8q-pcie";
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reg = <0x5f000000 0x10000>,
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<0x4ff00000 0x80000>;
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reg-names = "dbi", "config";
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ranges = <0x81000000 0 0x00000000 0x4ff80000 0 0x00010000>,
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<0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>;
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#interrupt-cells = <1>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#address-cells = <3>;
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#size-cells = <2>;
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clocks = <&pciea_lpcg IMX_LPCG_CLK_6>,
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<&pciea_lpcg IMX_LPCG_CLK_4>,
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<&pciea_lpcg IMX_LPCG_CLK_5>;
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clock-names = "dbi", "mstr", "slv";
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bus-range = <0x00 0xff>;
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device_type = "pci";
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interrupt-map = <0 0 0 1 &gic 0 73 4>,
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<0 0 0 2 &gic 0 74 4>,
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<0 0 0 3 &gic 0 75 4>,
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<0 0 0 4 &gic 0 76 4>;
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interrupt-map-mask = <0 0 0 0x7>;
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num-lanes = <1>;
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num-viewport = <4>;
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power-domains = <&pd IMX_SC_R_PCIE_A>;
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fsl,max-link-speed = <3>;
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status = "disabled";
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};
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pcieb: pcie@5f010000 {
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compatible = "fsl,imx8q-pcie";
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reg = <0x5f010000 0x10000>,
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<0x8ff00000 0x80000>;
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reg-names = "dbi", "config";
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ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>,
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<0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>;
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#interrupt-cells = <1>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#address-cells = <3>;
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#size-cells = <2>;
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clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>,
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<&pcieb_lpcg IMX_LPCG_CLK_4>,
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<&pcieb_lpcg IMX_LPCG_CLK_5>;
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clock-names = "dbi", "mstr", "slv";
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bus-range = <0x00 0xff>;
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device_type = "pci";
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interrupt-map = <0 0 0 1 &gic 0 105 4>,
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<0 0 0 2 &gic 0 106 4>,
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<0 0 0 3 &gic 0 107 4>,
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<0 0 0 4 &gic 0 108 4>;
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interrupt-map-mask = <0 0 0 0x7>;
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num-lanes = <1>;
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num-viewport = <4>;
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power-domains = <&pd IMX_SC_R_PCIE_B>;
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fsl,max-link-speed = <3>;
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status = "disabled";
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};
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sata: sata@5f020000 {
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compatible = "fsl,imx8qm-ahci";
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reg = <0x5f020000 0x10000>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sata_lpcg IMX_LPCG_CLK_4>,
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<&sata_crr4_lpcg IMX_LPCG_CLK_4>;
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clock-names = "sata", "sata_ref";
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phy-names = "sata-phy", "cali-phy0", "cali-phy1";
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power-domains = <&pd IMX_SC_R_SATA_0>;
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/*
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* Since "REXT" pin is only present for first lane PHY
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* and its calibration result will be stored, and shared
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* by the PHY used by SATA.
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*
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* Add the calibration PHYs for SATA here, although only
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* the third lane PHY is used by SATA.
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*/
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phys = <&hsio_phy 2 PHY_TYPE_SATA 0>,
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<&hsio_phy 0 PHY_TYPE_PCIE 0>,
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<&hsio_phy 1 PHY_TYPE_PCIE 1>;
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status = "disabled";
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};
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pciea_lpcg: clock-controller@5f050000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5f050000 0x10000>;
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clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>;
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clock-output-names = "hsio_pciea_mstr_axi_clk",
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"hsio_pciea_slv_axi_clk",
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"hsio_pciea_dbi_axi_clk";
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power-domains = <&pd IMX_SC_R_PCIE_A>;
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};
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sata_lpcg: clock-controller@5f070000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5f070000 0x10000>;
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clocks = <&hsio_axi_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "hsio_sata_clk";
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power-domains = <&pd IMX_SC_R_SATA_0>;
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};
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phyx2_lpcg: clock-controller@5f080000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5f080000 0x10000>;
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clocks = <&hsio_refa_clk>, <&hsio_per_clk>,
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<&hsio_refa_clk>, <&hsio_per_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
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clock-output-names = "hsio_phyx2_pclk_0",
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"hsio_phyx2_pclk_1",
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"hsio_phyx2_apbclk_0",
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"hsio_phyx2_apbclk_1";
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power-domains = <&pd IMX_SC_R_SERDES_0>;
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};
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phyx1_lpcg: clock-controller@5f090000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5f090000 0x10000>;
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clocks = <&hsio_refa_clk>, <&hsio_per_clk>,
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<&hsio_per_clk>, <&hsio_per_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>;
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clock-output-names = "hsio_phyx1_pclk",
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"hsio_phyx1_epcs_tx_clk",
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"hsio_phyx1_epcs_rx_clk",
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"hsio_phyx1_apb_clk";
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power-domains = <&pd IMX_SC_R_SERDES_1>;
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};
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phyx2_crr0_lpcg: clock-controller@5f0a0000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5f0a0000 0x10000>;
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clocks = <&hsio_per_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "hsio_phyx2_per_clk";
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power-domains = <&pd IMX_SC_R_SERDES_0>;
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};
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pciea_crr2_lpcg: clock-controller@5f0c0000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5f0c0000 0x10000>;
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clocks = <&hsio_per_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "hsio_pciea_per_clk";
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power-domains = <&pd IMX_SC_R_PCIE_A>;
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};
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sata_crr4_lpcg: clock-controller@5f0e0000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5f0e0000 0x10000>;
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clocks = <&hsio_per_clk>;
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#clock-cells = <1>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "hsio_sata_per_clk";
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power-domains = <&pd IMX_SC_R_SATA_0>;
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};
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hsio_phy: phy@5f180000 {
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compatible = "fsl,imx8qm-hsio";
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reg = <0x5f180000 0x30000>,
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<0x5f110000 0x20000>,
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<0x5f130000 0x30000>,
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<0x5f160000 0x10000>;
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reg-names = "reg", "phy", "ctrl", "misc";
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clocks = <&phyx2_lpcg IMX_LPCG_CLK_0>,
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<&phyx2_lpcg IMX_LPCG_CLK_1>,
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<&phyx2_lpcg IMX_LPCG_CLK_4>,
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<&phyx2_lpcg IMX_LPCG_CLK_5>,
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<&phyx1_lpcg IMX_LPCG_CLK_0>,
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<&phyx1_lpcg IMX_LPCG_CLK_1>,
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<&phyx1_lpcg IMX_LPCG_CLK_2>,
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<&phyx1_lpcg IMX_LPCG_CLK_4>,
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<&phyx2_crr0_lpcg IMX_LPCG_CLK_4>,
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<&phyx1_crr1_lpcg IMX_LPCG_CLK_4>,
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<&pciea_crr2_lpcg IMX_LPCG_CLK_4>,
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<&pcieb_crr3_lpcg IMX_LPCG_CLK_4>,
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<&sata_crr4_lpcg IMX_LPCG_CLK_4>,
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<&misc_crr5_lpcg IMX_LPCG_CLK_4>;
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clock-names = "pclk0", "pclk1", "apb_pclk0", "apb_pclk1",
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"pclk2", "epcs_tx", "epcs_rx", "apb_pclk2",
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"phy0_crr", "phy1_crr", "ctl0_crr",
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"ctl1_crr", "ctl2_crr", "misc_crr";
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#phy-cells = <3>;
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power-domains = <&pd IMX_SC_R_SERDES_0>, <&pd IMX_SC_R_SERDES_1>;
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status = "disabled";
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};
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};
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