185 lines
7.0 KiB
YAML
185 lines
7.0 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/fsl,imx35-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale IMX35/IMX5x/IMX6 IOMUX Controller
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maintainers:
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- Dong Aisheng <aisheng.dong@nxp.com>
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description:
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Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
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for common binding part and usage.
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allOf:
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- $ref: pinctrl.yaml#
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,imx35-iomuxc
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- fsl,imx51-iomuxc
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- fsl,imx53-iomuxc
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- fsl,imx6dl-iomuxc
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- fsl,imx6q-iomuxc
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- fsl,imx6sl-iomuxc
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- fsl,imx6sll-iomuxc
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- fsl,imx6sx-iomuxc
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- fsl,imx6ul-iomuxc
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- fsl,imx6ull-iomuxc-snvs
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- items:
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- const: fsl,imx50-iomuxc
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- const: fsl,imx53-iomuxc
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reg:
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maxItems: 1
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# Client device subnode's properties
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patternProperties:
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'grp$':
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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fsl,pins:
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description:
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each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
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be found in <arch/arm/boot/dts/nxp/imx/imx*-pinfunc.h>. The last integer
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CONFIG is the pad setting value like pull-up on this pin. Please
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refer to matching i.MX Reference Manual for detailed CONFIG settings.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: |
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"mux_reg" indicates the offset of mux register.
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- description: |
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"conf_reg" indicates the offset of pad configuration register.
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- description: |
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"input_reg" indicates the offset of select input register.
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- description: |
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"mux_val" indicates the mux value to be applied.
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- description: |
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"input_val" indicates the select input value to be applied.
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- description: |
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"pad_setting" indicates the pad configuration value to be applied.
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Common i.MX35
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PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13)
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PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13)
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PAD_CTL_HYS (1 << 8)
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PAD_CTL_PKE (1 << 7)
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PAD_CTL_PUE (1 << 6)
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PAD_CTL_PUS_100K_DOWN (0 << 4)
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PAD_CTL_PUS_47K_UP (1 << 4)
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PAD_CTL_PUS_100K_UP (2 << 4)
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PAD_CTL_PUS_22K_UP (3 << 4)
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PAD_CTL_ODE_CMOS (0 << 3)
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PAD_CTL_ODE_OPENDRAIN (1 << 3)
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PAD_CTL_DSE_NOMINAL (0 << 1)
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PAD_CTL_DSE_HIGH (1 << 1)
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PAD_CTL_DSE_MAX (2 << 1)
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PAD_CTL_SRE_FAST (1 << 0)
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PAD_CTL_SRE_SLOW (0 << 0)
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Common i.MX50/i.MX51/i.MX53 bits
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PAD_CTL_HVE (1 << 13)
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PAD_CTL_HYS (1 << 8)
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PAD_CTL_PKE (1 << 7)
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PAD_CTL_PUE (1 << 6)
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PAD_CTL_PUS_100K_DOWN (0 << 4)
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PAD_CTL_PUS_47K_UP (1 << 4)
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PAD_CTL_PUS_100K_UP (2 << 4)
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PAD_CTL_PUS_22K_UP (3 << 4)
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PAD_CTL_ODE (1 << 3)
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PAD_CTL_DSE_LOW (0 << 1)
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PAD_CTL_DSE_MED (1 << 1)
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PAD_CTL_DSE_HIGH (2 << 1)
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PAD_CTL_DSE_MAX (3 << 1)
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PAD_CTL_SRE_FAST (1 << 0)
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PAD_CTL_SRE_SLOW (0 << 0)
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Common i.MX6 bits
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PAD_CTL_HYS (1 << 16)
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PAD_CTL_PUS_100K_DOWN (0 << 14)
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PAD_CTL_PUS_47K_UP (1 << 14)
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PAD_CTL_PUS_100K_UP (2 << 14)
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PAD_CTL_PUS_22K_UP (3 << 14)
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PAD_CTL_PUE (1 << 13)
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PAD_CTL_PKE (1 << 12)
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PAD_CTL_ODE (1 << 11)
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PAD_CTL_SPEED_LOW (0 << 6)
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PAD_CTL_SPEED_MED (1 << 6)
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PAD_CTL_SPEED_HIGH (3 << 6)
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PAD_CTL_DSE_DISABLE (0 << 3)
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PAD_CTL_SRE_FAST (1 << 0)
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PAD_CTL_SRE_SLOW (0 << 0)
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i.MX6SL/MX6SLL specific bits
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PAD_CTL_LVE (1 << 22) (MX6SL/SLL only)
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i.MX6SLL/i.MX6SX/i.MX6UL/i.MX6ULL specific bits
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PAD_CTL_DSE_260ohm (1 << 3)
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PAD_CTL_DSE_130ohm (2 << 3)
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PAD_CTL_DSE_87ohm (3 << 3)
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PAD_CTL_DSE_65ohm (4 << 3)
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PAD_CTL_DSE_52ohm (5 << 3)
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PAD_CTL_DSE_43ohm (6 << 3)
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PAD_CTL_DSE_37ohm (7 << 3)
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i.MX6DL/i.MX6Q/i.MX6SL specific bits
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PAD_CTL_DSE_240ohm (1 << 3)
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PAD_CTL_DSE_120ohm (2 << 3)
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PAD_CTL_DSE_80ohm (3 << 3)
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PAD_CTL_DSE_60ohm (4 << 3)
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PAD_CTL_DSE_48ohm (5 << 3)
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PAD_CTL_DSE_40ohm (6 << 3)
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PAD_CTL_DSE_34ohm (7 << 3)
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required:
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- fsl,pins
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additionalProperties: false
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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iomuxc: pinctrl@20e0000 {
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compatible = "fsl,imx6ul-iomuxc";
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reg = <0x020e0000 0x4000>;
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mux_uart: uartgrp {
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fsl,pins = <
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0x0084 0x0310 0x0000 0 0 0x1b0b1
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0x0088 0x0314 0x0624 0 3 0x1b0b1
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>;
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};
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};
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- |
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iomuxc_snvs: pinctrl@2290000 {
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compatible = "fsl,imx6ull-iomuxc-snvs";
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reg = <0x02290000 0x4000>;
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pinctrl_snvs_usbc_det: snvsusbcdetgrp {
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fsl,pins = <
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0x0010 0x0054 0x0000 0x5 0x0 0x130b0
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>;
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};
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};
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- |
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iomuxc_mx6q: pinctrl@20e0000 {
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compatible = "fsl,imx6q-iomuxc";
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reg = <0x20e0000 0x4000>;
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pinctrl_uart4: uart4grp {
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fsl,pins =
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<0x288 0x658 0x000 0x3 0x0 0x140>,
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<0x28c 0x65c 0x938 0x3 0x3 0x140>;
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};
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};
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